A High Speed DAC Architecture for Continuous Time Pipeline ADC

Abstract

This
thesis provides an investigation of the architecture and the design of the
coarse DACs in continuous time pipeline (CTP) ADC to achieve high SFDR
performance within a large bandwidth at sampling frequency of 4.8 GHz
in TSMC 28nm technology.

Mismatch
errors of the coarse DACs in CTP ADC are very critical as they introduce
distortion and leak the quantization noise of the coarse stages to the output.
Conventional calibration techniques such as dynamic element matching (DEM)
linearize the DACs by converting the DAC distortion to white noise. However,
after the linearization, the residual gain errors of the DACs remain. As a
result, the quantization noise of the coarse quantizers leak to the output and
degrade the performance of the CTP. Therefore, the residual gain errors of the
DACs need to be estimated and calibrated. A resistive DAC architecture is
proposed in the first stage of the CTP. The proposed architecture employs
conventional DEM technique and is verified within the first stage of the
CTP. 

Furthermore,
two new innovative techniques are presented in this thesis. The first
technique, advanced dynamic element matching (ADEM), translates both the
distortion and the gain errors due to element mismatch of the DACs in
multi-stage CTP ADC into white noise. The second technique, advanced data
weighted averaging (ADWA), noise shapes both the the distortion and the gain
errors of the DACs. Therefore, the presented techniques do not require
additional digital calibration for element mismatch errors. Finally, a DAC
architecture is presented that allows a feasible implementation of the
presented techniques. The techniques are verified using simulations in MATLAB
and Cadence. However, The presented techniques require the CTP stages to have
equal impedances.