This work presents a highly linear quadrature down-converter topology intended for the linearization of digital Transmitters(DTX). By integrating it with a DTX, a fully integrated on-chip output-signal correction loop comes closer to its realization. The proposed down conversion architecture can measure the errors introduced by the non-linearity of the transmitter, rather than the transmitter output itself. These errors are determined by comparing the downconverted transmitter output signals with its analog ideal baseband I and Q reference signals. The reference signals are provided by low-power digital-to-analog converters(DACs), using the same IQ data input as the power DTX. This approach reduces the resolution/dynamic range requirements on the trans-impedance-amplifier (TIA) and analog-to-digital converters(ADCs) since the error signals have a reduced dynamic range compared to the transmitter’s output signal itself. These lower requirements on the ADCs and elimination of off-chip couplers and filter sease the integration of a complete digital pre-distortion (DPD) correction loop in future DTX implementations. As the core of this thesis work, a linear harmonic rejection mixer was designed. It uses resistors inits mixer branches to implement the proper currenct scaling needed for harmonic rejection (HR). The resulting HR mixer avoids the unwanted down-conversion of the higher harmonics of the DTX to the base band frequencies of interest. Also, atrans-impedance amplifier was designed with the proposed passive mixer. These TIAs are based on an inverter topology for maximum tranconductance and were biased for optimal linearity and offered a bandwidth over 1.8GHz. The proposed DTX error-detection architectureis implemented in the current domain. Performing the subtraction before the TIA drastically reduces the voltage swing at the input of the TIA, benefiting the linearity of the mixer and reference DAC. The overall HR-mixer configuration is simulated for its linearity, yielding an IIP3 of 49dBm, which to the best of the author’s knowledge, is the best-reported linearity for high bandwidth down-converting applications.

This report details the design and implementation of subsystems within a wireless FM transceiver. All the subsystems will be developed and integrated into a working FM transceiver. The subsystems discussed in this report are the modulator and demodulator. The modulator, on the transmitter side, varies the carrier wave frequency, based on the input audio signal. The demodulator, on the receiver side, can detect these variations and retrieve the audio signal. The modulator is implemented using a voltage controlled oscillator, which is based on the Colpitts oscillator. The input audio signal controls the oscillation frequency by modulating varicaps. The demodulator consists of mixer, amplifier and a slope detector. The amplifier is not discussed in this thesis. The mixer uses a local oscillator to shift the RF input signal to an intermediate frequency. This thesis proposes a mixer integrated into a local oscillator, using only one transistor. The detector is based on a slope detector, which differentiates the FM signal and converts it into an AM signal. The differentiator is implemented using a bandpass filter. The audio signal is retrieved from the AM signal using an envelope detector. The work will be concluded with a display of the complete FM transceiver circuit.