Designers typically add design margins to compensate for chip aging. However, this leads to yield loss (in case of overestimation) or low reliability (in case of underestimation). This paper analyzes the impact of aging on a complete high-performance industrial 14-nm FinFET SRAM. It investigates the impact on the memory’s parametric (i.e., its delay) and functional (i.e., correct functionality) metrics. Moreover, it examines which components are the main contributors to the degradation of the memory’s reliability and how it is impacted by workload and environmental conditions, i.e., temperature and voltage fluctuations. This paper not only investigates the impact of the memory’s components individually, which is typically the case in prior work, but it also studies the contribution of components’ interaction to the overall memory aging. The results show that the timing circuit, address decoder, and the output latches and buffers are the main contributors to the memory’s parametric degradation, while the cell, sense amplifier, and address decoder are the main contributors to its functional degradation. Moreover, the results show that it is crucial to consider the impact of the interaction of components on the aging; individual analysis leads to overly pessimistic results and even wrong conclusions in certain cases.@en

Memory designs typically contain design margins to compensate for aging. As aging impact becomes more severe with technology scaling, it is crucial to accurately predict such impact to prevent overestimation or underestimation of the margins. This paper proposes a methodology to accurately and efficiently analyze the impact of aging on the memory's digital logic (e.g., timing circuit and address decoder) while considering realistic workloads extracted from applications. To demonstrate the superiority of the methodology, we analyzed the degradation of the L1 data and instruction caches for an ARM v8-a processor using both our methodology as well as the state-of-the-art methods. The results show that the existing methods may significantly over-or underestimate the impact (e.g., the decoder margin up to 221% and the access time up to 20%) as compared with the proposed scheme. In addition, the results show that in general the instruction cache has the highest degradation. For example, its access time degrades up to 9% and its decoder margin up to 44%.

@en

Designers typically add design margins to memories to compensate for their aging. As the aging impact increases with technology scaling, bigger margins become necessary. However, this negatively impacts area, yield, performance, and power consumption. Alternatively, mitigation schemes can be used to reduce the impact of aging. This paper proposes a hardware-based mitigation scheme for the memory's address decoder logic. The scheme is based on adapting the decoder's workload during idle cycles by stressing the short paths and putting long paths into relaxation. Thanks to the adapted workload, the impact of aging on the address decoder is reduced, resulting in a more reliable memory. To validate the benefit of the mitigation scheme, the decoder's degradation of the L1 data and instruction caches for an ARM v8-a processor is analyzed. The experimental results show that the proposed mitigation scheme reduces the degradation of the decoder's timing margin with up to 4.1x at negligible area and no more than 3% power overhead.@en

Integrated circuits typically contain design margins to compensate for aging. As aging impact increases with technology scaling, bigger margins are necessary to achieve the desired reliability. However, these increased margins lead to a reduced performance and lower yield. Alternatively, mitigation schemes can be deployed to reduce the aging. This paper proposes a software-based method to mitigate the aging of the memory's address decoder logic due to Bias Temperature Instability. The method is based on periodically applying a rejuvenation application on top of a user application. The goal of the rejuvenation application is to recover aged transistors of the critical paths of the address decoder. The experimental results show that the proposed method significantly reduces aging in cases when applications consist of memory access patterns that result in an unbalanced stress in the address decoder logic. In particular, it reduces the degradation of the address decoder's setup delay by up to 43% with an execution overhead of only 1%.@en

This paper presents an accurate technique to extensively analyze the impact of time-zero (i.e., global and local variation) and time-dependent (i.e., voltage, temperature, workload, and aging) variation on the offset voltage specification of a memory sense amplifier design using 45 nm predictive technology model (PTM) high performance library. The results show that increasing the supply voltage both for time-zero and time-dependent reduces the offset voltage specification marginally, irrespective of the process corners. In contrast, the offset voltage specification is very sensitive to the temperature and the workload, i.e., the applied voltage patterns. The results also show that a balanced workload results in a significantly lower offset voltage specification. The above results can be used to estimate the required offset voltage accurately for a given lifetime, and operational conditions such as workload, temperature, and voltage; hence, enable the designer to take appropriate measures for a high quality, robust, optimal and reliable design.

@en

Memory designs usually add design margins to compensate for chip aging; this may lead to yield and performance loss (in case of overestimation) or reduced reliability (in case of underestimation). This paper analyzes the impact of aging on cutting edge high performance 14nm FinFET SRAM using a calibrated aging model; it does not only analyze the impact of the SRAM's components individually, as it is the case in prior work, but it also investigates the contribution of the interaction of these components while considering different workloads; both the overall metric of the memory (i.e., the access time) as well as metrics of individual components (e.g., sensing delay for the sense amplifier) are examined. The results show that it is crucial to consider not only the aging of all individual components, but also their interaction in order to provide accurate prediction of aging effects; considering only aging of single/individual components leads to either too optimistic or pessimistic results. For example, using our approach (which includes the components interaction) results approximately in 9.1% degradation of memory access time (for three years of aging), while using the traditional approach (based on adding the impact of individual components) results in 7.3% increase only; a relative difference of 25%, for which the timing and the address decoder components are the main contributors. With respect to individual components, the sense amplifier is the most fragile one (e.g., its offset voltage spec. degrades up to 58%).@en

This paper proposes an appropriate method to estimate and mitigate the impact of aging on the read path of a high performance SRAM design; it analyzes the impact of the memory cell, and sense amplifier (SA), and their interaction. The method considers different workloads, technology nodes, and inspects both the bit-line swing (BLS) (which reflect the degradation of the cell) and the sensing delay (SD) (which reflects the degradation of the sense amplifier); the voltage swing on the bit lines has a direct impact on the proper functionality of the sense amplifier. The results with respect to the quantification of the aging, show for the considered SRAM read-path design that the cell degradation is marginal as compared to the sense amplifier, while the SD degradation strongly depends on the workload, supply voltage, temperature, and technology nodes (up to 41% degradation). The mitigation schemes, one targeting the cell and one the sense amplifier, confirm the same and show that sense amplifier mitigation (up to 15.2% improvement) is more effective for the SRAM read path than cell mitigation (up to 11.4% improvement).

@en

Complementary Metallic Oxide Semiconductor (CMOS) technology scaling enhances the performance, transistor density, functionality, and reduces cost and power consumption. However, scaling causes significant reliability challenges both from a manufacturing and operational point of view. Obtaining reliable memories require accurate understanding of the impact of aging (such as Bias temperature instability (BTI)) on individual memory components and how they interact with each other. In this dissertation, two types of challenges are addressed, which are related to BTI aging and partially to mitigation schemes: one related to the aging of sense amplifier and another one to the aging of read path and write path. Analysis of aging impact on different memory sense amplifiers - The analysis of BTI impact on various memory sense amplifier (SA) designs was performed, while taking into account two BTI models (i.e., Atomistic and RD model), different technology nodes (i.e., 90, 65, 45, 32, 22, and 16 nm), and different workloads. First, the analysis and comparison of RD and Atomistic models impact on the SA were performed. The results show that the atomistic trap-based BTI model is more accurate than the RD model. Second, the investigation of BTI impact on the drain-input latch type SA for various technology nodes and supply voltages was performed. The result shows that as technology scales down, the impact of BTI on sensing delay increases, while the sensing voltage decreases, causing less robust and reliable memory sense amplifier. The result also shows that increase in supply voltage compensates the BTI degradation. Third, an accurate technique was proposed and characterized for the integral impact of BTI and voltage temperature variation on the memory standard latch type SA for various technology nodes and workloads. The results show that the degradation is strongly dependent on workload and temperature. Fourth, in addition to the latter, the impact of process variation at timezero was incorporated and analyzed. The results show that the SA sensing delay degradation is more significant at lower nodes and could lead to read failures at lower power supply. This reveals that there must be a tradeoff between performance and reliability. Fifth, an accurate methodology was proposed to quantify the impact of variability on the memory SA offset-voltage for both time-zero and time-dependent variability. The results show that the impact on the offset voltage specification is significant for aging time-dependent variability. Sixth, on top of the latter, the sensitivity of the SA and its failure rate were analyzed for five process corners (i.e., Nominal, Fast-Fast, Fast-Slow, Slow-Fast, and Slow-Slow). The results show that balanced workloads result in a significant low offset voltage specification. Finally, the impact of aging was analyzed and compared, while considering different supply voltages, temperatures, and SA designs. The results show that the High Performance SA degrades faster than other SA types, irrespective of the workload, supply voltage, and temperature. Investigation of read path aging - Adequate techniques was proposed to estimate and mitigate the impact of aging on the read path of a high performance SRAMmemory. The mitigation techniques are based on the re-sizing of the pull-down transistors of the cell’s and the SA’s designs. The results show that the SA mitigation is more effective for the SRAM read path (i.e., SA) than cell mitigation. Investigation of write path aging - The analysis of BTI impact on the SRAM write driver was performed for various supply voltages, temperatures, and technology nodes. The result shows that the impact of BTI increases the write delay and widen its distribution, when the technology scales down. @en

Designers typically add design margins to compensate for time-zero variability (due to process variation) and time-dependent (due to, e.g., bias temperature instability) variability. These variabilities become worse with scaling, which leads to larger design margin requirements. As an alternative, mitigation schemes can be applied to counteract the variability. This paper investigates the impact of aging on the offset voltage of the memory's sense amplifier (SA). For the analysis, the degradation of the SAs in the L1 data and instruction caches of an ARM processor is quantified while using realistic workloads extracted from the SPEC CPU2006 Benchmark suite. Furthermore, the effect of our mitigation scheme, i.e., an online control circuit that balances the SA workload, is analyzed. The simulation results show that the mitigation scheme reduces the offset voltage degradation due to aging with up to 40% for the benchmarks, depending on the stress conditions (temperature, voltage, and workload).@en

The CMOS technology scaling faced over the past recent decades severe variability and reliability challenges. One of the major reliability challenges is bias temperature instability (BTI). This paper analyzes the impact of BTI on the sensing delay of standard latch-type sense amplifier (SA), which is one of the critical components of high performance memories; the analysis is done by incorporating the impact of process, voltage, and temperature variations (in order to investigate the severity of the integral impact) and by considering different workloads and four technology nodes (i.e., 45, 32, 22, and 16 nm). The results show the importance of taking the SA degradation into consideration for robust memory design; the SA degradation depends on the application and technology node, and the sensing delay can increase with 184.58% for the worst case conditions at 16 nm. The results also show that the BTI impact for nominal conditions at 16 nm reaches a 12.10% delay increment. On top of that, when extrinsic conditions are considered, the degradation can reach up to 168.45% at 398 K for 16 nm.

@en

To compensate for time-zero (due to process variation) and time-dependent (due to e.g. Bias Temperature Instability (BTI)) variability, designers usually add design margins. Due to technology scaling, these variabilities become worse, leading to the need for bigger design margins. Typically, only worst-case scenarios are considered, which will not present the actual workload of the targeted application. Alternatively, mitigation schemes can be used to counteract the variability. This paper presents a run-time design-for-reliability scheme for memory Sense Amplifiers (SAs); SAs are an integral part of any memory system and are very critical for high performance. The proposed scheme mitigates the impact of time-dependent variability due to aging by using an on-line control circuit to create a balanced workload. The simulation results show that the proposed scheme can reduce the most critical figures-of-merit, namely the offset voltage shift and the sensing delay of the SA with up to ~40% and ~10%, respectively, depending on the stress conditions (temperature, voltage, workload).@en

This paper investigates the impact of aging in the read path of 32nm high performance SRAM; it combines the impact on the memory cell, on the sense amplifier, and on the way they interact. The analysis is done while considering different workloads and by inspecting both the bit-line swing (which reflect
the degradation of the cell) and the sensing delay (which reflects the degradation of the sense-amplifier); the voltage swing on the bit lines has a direct impact on the proper functionality of the sense amplifier. The results show that in addition to the sense amplifier degradation, the cell degradation also contributes to the sensing delay increase; the share of this contribution depends on the cell design. Moreover, this sensing delay becomes worst at
stressy workloads.@en

With the continuous downscaling of CMOS technologies, ICs become more vulnerable to transistor aging mainly due to Bias Temperature Instability (BTI). This paper presents a comparative study of the BTI impact while considering varying supply voltages and temperatures for three memory sense amplifier (SA) designs: low power (LP), mid power/performance (MP), and high performance (HP). As an evaluation metric, the sensing delay (SD) of the three designs is analyzed for various workloads using 45nm technology. The results show that HP SA degrades faster than MP SA and LP SA irrespective of the workload, supply voltage, and temperature. At nominal supply voltage and temperature, HP degrades up to 1.62x faster than MP, and up to 1.94x faster than LP designs for the worst case workload. In addition, the results show that an increase of 10% in power supply has a marginal impact on the relative degradation. In contrast, the results show that a temperature increment significantly worsens the BTI impact. Finally, the results show that for 16nm technology, BTI impact becomes worse and even causes read failures. This clearly indicates that designing for reliability is not only strongly application dependent, but also technology node dependent. Hence, one has to carefully consider the targeted application, design, and technology node in order to provide appropriate solutions.@en

Nowadays, typical (memory) designers add design margins to compensate for uncertainties, however, this may be overestimated leading to yield loss, or underestimated leading to reduced reliability designs. Accurate quantification of all uncertainties is therefore critical to provide high quality and optimal designs. These uncertainties are caused by zero-time variability (due to process variability), and by run-time variability(due to environmental variabilities such as voltage and temperature, or due to temporal variability such as aging). This paper uses an accurate methodology to predict the impact of both zero-and run-time variability on the offset voltage of sense amplifiers while considering different workloads and PVT variations for a pre-defined failure rate. The results show a marginal impact of environmental run-time variability on the offset specification when considering zero-time variability only, while this becomes significant (up to 2X) when incorporating aging run-time variability. The results can be used to quantify whether the required offset voltage is met or not for the targeted lifetime, hence, enable the designer to take appropriate measures for an efficient and optimized design, depending on the targeted application lifetime.@en

Bias Temperature Instability (BTI) has become a major reliability challenge for nano-scaled devices. This paper presents BTI analysis for the SRAM write driver. Its evaluation metric, the write delay (WD), is analyzed for various supply voltages and temperatures for three technology nodes, i.e., 45nm, 32nm, and 22nm. The results show that as technology scales down, BTI impact on write delay (i.e., its average and +/- 3σ variations) increases; the 22nm design can degrade up to 1.9x more than the 45nm design at nominal operation conditions. In addition, the result shows that an increment in supply voltage (i.e., from -10% Vdd to +10% Vdd) increases the relative write delay during the operational lifetime. Furthermore, the results show that a temperature increment accelerates the BTI induced write delay significantly; while at 298K the degradation is up to 4.7%, it increases to 41.4% at 398K for the 22nm technology node.@en