Read Path Degradation Analysis in SRAM

Conference paper (2016)

Authors

I.O. Agbo Computer Engineering - EEMCS
M. Taouil Computer Engineering - EEMCS
S. Hamdioui Computer Engineering - EEMCS
P Weckx IMEC
W Dehaene Katholieke Universiteit Leuven
Research Group
Computer Engineering (EEMCS) (TU Delft)
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Published Date

2016

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Quantum & Computer Engineering

Research Group

Computer Engineering

Abstract

This paper investigates the impact of aging in the read path of 32nm high performance SRAM; it combines the impact on the memory cell, on the sense amplifier, and on the way they interact. The analysis is done while considering different workloads and by inspecting both the bit-line swing (which reflect
the degradation of the cell) and the sensing delay (which reflects the degradation of the sense-amplifier); the voltage swing on the bit lines has a direct impact on the proper functionality of the sense amplifier. The results show that in addition to the sense amplifier degradation, the cell degradation also contributes to the sensing delay increase; the share of this contribution depends on the cell design. Moreover, this sensing delay becomes worst at
stressy workloads.