Level-crossing analog-To-digital converters (LC-ADCs) are neuromorphic, event-driven data converters that are gaining much attention for resource-constrained applications where intelligent sensing must be provided at the extreme edge, with tight energy and area budgets. LC-ADCs translate real-world analog signals (such as ECG, EEG, etc.) into sparse spiking signals, providing significant data bandwidth reduction and inducing savings of up to two orders of magnitude in area and energy consumption at the system level compared to the use of conventional ADCs. In addition, the spiking nature of LC-ADCs make their use a natural choice for ultra-low-power, event-driven spiking neural networks (SNNs). Still, the compressed nature of LC-ADC spiking signals can jeopardize the performance of downstream tasks such as signal classification accuracy, which is highly sensitive to the LC-ADC tuning parameters. In this paper, we explore the use of popular information criteria found in model selection theory for the tuning of the LC-ADC parameters. We experimentally demonstrate that information metrics such as the Bayesian, Akaike and corrected Akaike criteria can be used to tune the LC-ADC parameters in order to maximize downstream SNN classification accuracy. We conduct our experiments using both full-resolution weights and 4-bit quantized SNNs, on two different bio-signal classification tasks. We believe that our findings can accelerate the tuning of LC-ADC parameters without resorting to computationally-expensive grid searches that require many SNN training passes.

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This paper optimizes the MNEMOSENE architecture, a compute-in-memory (CiM) tile design integrating computation and storage for increased efficiency. We identify and address bottlenecks in the Row Data (RD) buffer that cause losses in performance. Our proposed approach includes mitigating these buffering bottlenecks and extending MNEMOSENE’s single-tile design to a multi-tile configuration for improved parallel processing. The proposal is validated through comprehensive analyses exploring the mapping of diverse neural networks evaluated on CiM crossbar arrays based on NVM technologies. These proposed enhancements lead up to 55% reduction in execution time compared to the original single-tile architecture for any general matrix multiplication (GEMM) operation. Our evaluation shows that while ReRAM and PCM offer notable energy advantages, their integration with scaled CMOS is limited, which leads to VGSOT-MRAM emerging as a promising alternative due to its good balance between energy efficiency and superior integration capabilities. The VGSOT-MRAM crossbar arrays provide 12×,49×, and 346× more energy efficiency than PCM, ReRAM, and STT-MRAM ones, respectively. It translates, on average for the considered workload, in 1.5×,3×, and 14.5× better energy efficiency of the entire system.@en

Computation-in-Memory (CIM) is an emerging computing paradigm to address memory bottleneck challenges in computer architecture. A CIM unit cannot fully replace a general-purpose processor. Still, it significantly reduces the amount of data transfer between a traditional memory unit and the processor by enriching the transferred information. Data transactions between processor and memory consist of memory access addresses and values. While the main focus in the field of in-memory computing is to apply computations on the content of the memory (values), the importance of CPU-CIM address transactions and calculations for generating the sequence of access addresses for data-dominated applications is generally overlooked. However, the amount of information transactions used for "address"can easily be even more than half of the total transferred bits in many applications. In this article, we propose a circuit to perform the in-memory Address Calculation Accelerator. Our simulation results showed that calculating address sequences inside the memory (instead of the CPU) can significantly reduce the CPU-CIM address transactions and therefore contribute to considerable energy saving, latency, and bus traffic. For a chosen application of guided image filtering, in-memory address calculation results in almost two orders of magnitude reduction in address transactions over the memory bus.

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Spin-transfer torque magnetic random access memory (STT-MRAM) based computation-in-memory (CIM) architectures have shown great prospects for an energy-efficient computing. However, device variations and non-idealities narrow down the sensing margin that severely impacts the computing accuracy. In this work, we propose an adaptive referencing mechanism to improve the sensing margin of a CIM architecture for boolean binary logic (BBL) operations. We generate reference signals using multiple STT-MRAM devices and place them strategically into the array such that these signals can address the variations and trace the wire parasitics effectively. We have demonstrated this behavior using an STT-MRAM model, which is calibrated using 1Mbit characterized array. Results show that our proposed architecture for binary neural networks (BNN) achieves up to 17.8 TOPS/W on the MNIST dataset and 130× performance improvement for the text encryption compared to the software implementation on Intel Haswell processor.

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With the rise of the Internet of Things (IoT), a huge market for so-called smart edge-devices is foreseen for millions of applications, like personalized healthcare and smart robotics. These devices have to bring smart computing directly where the data is generated, while coping with the limited energy budget. Conventional von-Neumann architecture fail to meet these requirements due to e.g., memory-processor data transfer bottleneck. Memristor-based computation-in-memory (CIM) has the potential to realize smart local computing for highly parallel data-dominated AI applications by exploiting the inherent properties of the architecture and the physical characteristics of the memristors. This paper provides a broad overview of CIM architecture highlighting its potential and unique properties in enabling smart local computing. Moreover, it discusses design considerations of such architectures including both crossbar array as well as peripheral circuits; special attention is given to analog-to-digital converter (ADC), as it is the most critical unit of analog-based CIM operation e.g., vector-matrix multiplication (VMM). Finally, the paper outlines the potential future directions for CIM-based edge smart computing.

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We propose a multi-time scale energy management framework for a smart photovoltaic (PV) system that can calculate optimized schedules for battery operation, power purchases, and appliance usage. A smart PV system is a local energy community that includes several buildings and households equipped with PV panels and batteries. However, due to the unpredictability and fast variation of PV generation, maintaining energy balance and reducing electricity costs in the system is challenging. Our proposed framework employs a model predictive control approach with a physics-based PV forecasting model and an accurately parameterized battery model. We also introduce a multi-time scale structure composed of two-time scales: a longer coarse-grained time scale for daily horizon with 15-minutes resolution and a shorter fine-grained time scale for 15-minutes horizon with 1-second resolution. In contrast to the current single-time scale approaches, this alternative structure enables the management of a necessary mix of fast and slow system dynamics with reasonable computational times while maintaining high accuracy. Simulation results show that the proposed framework reduces electricity costs up 48.1% compared with baseline methods. The necessity of a multi-time scale and the impact on accurate system modeling in terms of PV forecasting and batteries are also demonstrated.

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Designers typically add design margins to semiconductor memories to compensate for aging. However, the aging impact increases with technology downscaling, leading to the need for higher margins. This results into a negative impact on area, yield, performance, and power consumption. As an alternative, mitigation schemes can be developed to reduce such impact. This paper proposes a mitigation scheme for the memory's sense amplifier (SA); the scheme is based on creating a skew in the relative strengths of the SA's cross-coupled inverters during design. The skew is compensated by aging due to unbalanced workloads. As a result, the impact of aging on the SA is reduced. To validate the mitigation scheme, the degradation of the sense amplifier is analyzed for several workloads. The experimental results show that the proposed mitigation scheme reduces the degradation of the sense amplifier's critical figure-of-merit, the offset voltage, with up to 26%.

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Technological and architectural improvements have been constantly required to sustain the demand of faster and cheaper computers. However, CMOS down-scaling is suffering from three technology walls: leakage wall, reliability wall, and cost wall. On top of that, a performance increase due to architectural improvements is also
gradually saturating due to three well-known architecture walls: memory wall, power wall, and instruction level parallelism (ILP) wall. Hence, a lot of research is focusing on proposing and developing new technologies and architectures. In this article, we present a comprehensive classification of memory-centric computing architectures; it is based on three metrics: computation location, level of parallelism, and used memory technology. The classification not only provides an overview of existing architectures with their pros and cons but also unifies the terminology that uniquely identifies these architectures and highlights the potential future architectures that can be further explored. Hence, it sets up a direction for future research in the field.@en

As technology scales down, the impact of variability due to process variation and aging increases. In order to guarantee an optimal design with a low failure rate, it is crucial to take into account the impact of these sources of variability. Prior work on SRAM reliability has mainly focused on estimating the impact of this variability on the memory cell array, while the peripheral circuitry and the complete memory circuit have received little attention. This study analyzes the impact of aging on a complete 14nm FinFET SRAM circuit. In this analysis, it is investigated how the memory's individual components contribute to the memory's overall degradation. In addition, it is investigated how the application-dependent aging impacts the memory. The results of this work show that, depending on the investigated metric, the peripheral circuitry has a significantly higher contribution to the overall degradation of the memory than the cell array. In addition, the degradation of the memory is shown to be strongly dependent on the application. Overall, the results of this study emphasize that the impact of the peripheral circuitry and the application-dependent aging must be taken into account during design in order to optimally solve SRAM reliability.

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Designers typically add design margins to compensate for chip aging. However, this leads to yield loss (in case of overestimation) or low reliability (in case of underestimation). This paper analyzes the impact of aging on a complete high-performance industrial 14-nm FinFET SRAM. It investigates the impact on the memory’s parametric (i.e., its delay) and functional (i.e., correct functionality) metrics. Moreover, it examines which components are the main contributors to the degradation of the memory’s reliability and how it is impacted by workload and environmental conditions, i.e., temperature and voltage fluctuations. This paper not only investigates the impact of the memory’s components individually, which is typically the case in prior work, but it also studies the contribution of components’ interaction to the overall memory aging. The results show that the timing circuit, address decoder, and the output latches and buffers are the main contributors to the memory’s parametric degradation, while the cell, sense amplifier, and address decoder are the main contributors to its functional degradation. Moreover, the results show that it is crucial to consider the impact of the interaction of components on the aging; individual analysis leads to overly pessimistic results and even wrong conclusions in certain cases.@en

With the growing competition of utility-scale photovoltaic (PV) plants to provide electricity to the grid, accurate energy yield simulation is becoming essential. Apart from irradiance, forced convection can have an equally significant impact on solar cell temperature, which in turn affects the power output, hence the energy yield. As a consequence, the wind must be taken into account for an accurate estimation of PV installations' energy yield. However, no earlier studies have systematically investigated the impact of wind on precise energy yield simulation. In this study, we investigate how sensitive is PV module's output to forced convection. First, we reveal a significant deviation between the simulated PV module's energy yield and cell temperature compared to experimental results in case dynamic wind effects are neglected. Secondly, for controlled incremental forced convection with a steady state scenario, we show that for higher wind speed the change of PV module's cell temperature and power output is small with different forced convection. Whereas, for the low wind speed, small changes of forced convection imply a larger variation of the PV module's cell temperature and power output. This shows that for high wind speed region energy yield estimation is less sensitive on modelling errors. Whereas for the low wind speed region it is highly sensitive.

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Non-uniform conditions within a PV module lead to significant energy losses in conventional topologies. Some of the energy lost due to partial shading can be recovered by installing reconfigurable modules. In order to explore the potential benefits of reconfigurable topologies in installations where non-uniform conditions are dominant, three shading scenarios are simulated throughout the year, both for reconfigurable and conventional modules. This allows the evaluation of the performance of each topology and estimation of the long-term gains. Using a cost function, which includes the additional investment cost, the energy gain can be translated to financial terms. Through this, locations where reconfigurable topologies can be beneficial, both in energy and financial terms, can be identified. The methodology is applied to the case of reconfigurable PV modules with a snake-like configuration. Simulation results show that these PV modules allow for higher energy production compared to conventional modules under all the simulated shading scenarios. However, they remain economically profitable over 20 years only in locations where partial shading is expected to occur daily, either throughout the full year or at least in the period of the year where energy generation is high.

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Memory designs typically contain design margins to compensate for aging. As aging impact becomes more severe with technology scaling, it is crucial to accurately predict such impact to prevent overestimation or underestimation of the margins. This paper proposes a methodology to accurately and efficiently analyze the impact of aging on the memory's digital logic (e.g., timing circuit and address decoder) while considering realistic workloads extracted from applications. To demonstrate the superiority of the methodology, we analyzed the degradation of the L1 data and instruction caches for an ARM v8-a processor using both our methodology as well as the state-of-the-art methods. The results show that the existing methods may significantly over-or underestimate the impact (e.g., the decoder margin up to 221% and the access time up to 20%) as compared with the proposed scheme. In addition, the results show that in general the instruction cache has the highest degradation. For example, its access time degrades up to 9% and its decoder margin up to 44%.

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Today's computing architectures and device technologies are unable to meet the increasingly stringent demands on energy and performance posed by emerging applications. Therefore, alternative computing architectures are being explored that leverage novel post-CMOS device technologies. One of these is a Computation-in-Memory architecture based on memristive devices. This paper describes the concept of such an architecture and shows different applications that could significantly benefit from it. For each application, the algorithm, the architecture, the primitive operations, and the potential benefits are presented. The applications cover the domains of data analytics, signal processing, and machine learning. @en

Designers typically add design margins to memories to compensate for their aging. As the aging impact increases with technology scaling, bigger margins become necessary. However, this negatively impacts area, yield, performance, and power consumption. Alternatively, mitigation schemes can be used to reduce the impact of aging. This paper proposes a hardware-based mitigation scheme for the memory's address decoder logic. The scheme is based on adapting the decoder's workload during idle cycles by stressing the short paths and putting long paths into relaxation. Thanks to the adapted workload, the impact of aging on the address decoder is reduced, resulting in a more reliable memory. To validate the benefit of the mitigation scheme, the decoder's degradation of the L1 data and instruction caches for an ARM v8-a processor is analyzed. The experimental results show that the proposed mitigation scheme reduces the degradation of the decoder's timing margin with up to 4.1x at negligible area and no more than 3% power overhead.@en

This paper presents an accurate technique to extensively analyze the impact of time-zero (i.e., global and local variation) and time-dependent (i.e., voltage, temperature, workload, and aging) variation on the offset voltage specification of a memory sense amplifier design using 45 nm predictive technology model (PTM) high performance library. The results show that increasing the supply voltage both for time-zero and time-dependent reduces the offset voltage specification marginally, irrespective of the process corners. In contrast, the offset voltage specification is very sensitive to the temperature and the workload, i.e., the applied voltage patterns. The results also show that a balanced workload results in a significantly lower offset voltage specification. The above results can be used to estimate the required offset voltage accurately for a given lifetime, and operational conditions such as workload, temperature, and voltage; hence, enable the designer to take appropriate measures for a high quality, robust, optimal and reliable design.

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Device aging is an important concern in nanoscale designs. Due to aging the electrical behavior of transistors embedded in an integrated circuit deviates from original intended one. This leads to performance degradation in the underlying device, and the ultimate device failure. This effect is exacerbated in emerging technologies. To be able to tailor effective aging mitigation schemes and improve the reliability of devices realized in cutting edge technologies, there is a need to accurately study the effect of aging in high performance industrial applications. According, this paper targets a high performance SRAM memory realized in 14nm FinFET technology and depicts how aging degrades the individual components of this memory as well as the interaction between them. Aging mitigation is critical not only from device reliability point of view but also regarding device security perspectives. It is essential to assure the security of the sensitive tasks performed by the security-sensitive circuits and to guarantee the security of information stored within these devices in the presence of aging. Accordingly in this paper, we also focus on aging-related security concerns and present the cases in which aging need to considered to preserve security.@en

Memory designs usually add design margins to compensate for chip aging; this may lead to yield and performance loss (in case of overestimation) or reduced reliability (in case of underestimation). This paper analyzes the impact of aging on cutting edge high performance 14nm FinFET SRAM using a calibrated aging model; it does not only analyze the impact of the SRAM's components individually, as it is the case in prior work, but it also investigates the contribution of the interaction of these components while considering different workloads; both the overall metric of the memory (i.e., the access time) as well as metrics of individual components (e.g., sensing delay for the sense amplifier) are examined. The results show that it is crucial to consider not only the aging of all individual components, but also their interaction in order to provide accurate prediction of aging effects; considering only aging of single/individual components leads to either too optimistic or pessimistic results. For example, using our approach (which includes the components interaction) results approximately in 9.1% degradation of memory access time (for three years of aging), while using the traditional approach (based on adding the impact of individual components) results in 7.3% increase only; a relative difference of 25%, for which the timing and the address decoder components are the main contributors. With respect to individual components, the sense amplifier is the most fragile one (e.g., its offset voltage spec. degrades up to 58%).@en

Reconfigurable photovoltaic modules represent an effective solution to improve PV system resilience to partial shading. Indeed, the availability of different configurations increases energy generation under non-uniform conditions. However, the additional components that are active under uniform conditions lead to higher losses compared to equivalent static solutions. This paper presents a methodology for the design of optimized reconfigurable PV modules, balancing losses under uniform conditions and gain under partial shading. First, feasible reconfigurable module instantiations are selected given some design constraints. Then, the search space is further reduced by taking into account the typical operating conditions of the module. Finally, the best module layouts are chosen based on performance consideration. Results for a specific case study are presented to show the feasibility of the proposed methodology.

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PV module testing under standard conditions is an important and well-established procedure, which plays a vital role in module rating. However, PV modules rarely operate at standard conditions therefore their field performance should be predicted based on long term outdoor monitoring or by means of models – so called energy yield models, which combine PV module characteristics with varying environmental conditions. The present work employs a bottom-up, physics-based energy yield modelling approach, which accounts to the interacting optical, thermal and electrical mechanisms in a detailed manner. Additionally, measured data is used for the accurate calibration of the models. Such an approach permits to explore the influence of cell- and module technology details on energy yield under any specific environmental conditions. The present work employs such a method to evaluate the influence of Silicon solar cell technology on energy yield under desert and moderate climates, where the interplay of different irradiance and ambient temperature levels result in a challenging PV performance prediction problem. The purpose of this work is to identify the best-suited solar cell technologies and to understand the underlying mechanisms, which lead to superior PV performance under specific climate conditions. The study is performed by means of physics-based exploratory energy yield simulations with detailed resolution of the thermal effects. Our comparison of four different cell technologies in monofacial modules highlights that superior illumination-dependent performance can contribute to annual energy yield enhancement under both moderate and desert climates amounting to 1.75% and 0.4%, respectively; while a 0.04%/°C advantage in relative temperature coefficient increases annual energy yield (by 1.2%) only under a desert climate.

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