In the past several decades, tremendous progress has been made in physics and engineering towards realize practical quantum computers. Several small-scale systems have already been demonstrated which utilize separate, off-the-shelf hardware components to directly control qubits. However, as higher-quality qubits continue to spur the development of larger-scale systems capable of performing complex computations, it is becoming increasingly important to consider how control architectures should be adapted to keep pace. This motivates the design of a scalable control architecture capable of dynamically orchestrating quantum programs on a large number of qubits while maintaining the stringent requirements imposed by qubit coherence times and operation in dilution refrigerators.

In this thesis, several contributions are made towards realizing a control architecture for large-scale quantum computing systems based on distributed Nitrogen-vacancy (NV) centers in diamond. A configurable design is presented which significantly increases system throughput by parallelizing execution of instructions performed on separate distributed nodes. A detailed analysis of the dependencies between instructions in quantum programs at an algorithmic level is also used to develop an heuristic function for evaluating the performance of different hardware designs. Furthermore, the demand for increased complexity of computations is addressed by a microarchitectural design which translates high-level quantum instructions into a set of signals used to configure special-purpose signal generators. Taken together, these microarchitectural components enable highly-efficient generation of signals for performing arbitrary single-qubit rotation gates, a key step towards achieving universal quantum computation.

Additionally, detailed evaluations of the control architecture enhancements are provided. For example, run time analysis is performed on a set of benchmark quantum algorithms to show the significant speedup capabilities and performance tradeoffs of the control architecture's parallel execution model. Moreover, the successful integration of the control architecture with the pre-existing signal generators is verified by executing parameterized microinstructions which configure the signal generators to produce amplitude-modulated, phase-coherent microwave and radio-frequency signals. Finally, the full system functionality is verified using several microprograms which each implement higher-level quantum instructions for single-qubit rotation gates. These demonstrations bridge the end-to-end connection between quantum algorithms and physically-realizable quantum gates in hardware.

The increasing demand for data-intensive applications such as artificial intelligence and big data analytics is hitting the limitations of traditional computing architectures. Near-memory processing architectures, like UPMEM's Data Processing Units (DPUs), offer a promising solution by integrating computation with memory, reducing data movement and energy consumption. However, UPMEM's scratchpad-centric design imposes some critical programming challenges, requiring explicit programmer intervention for efficient memory management, which increases program complexity and limits portability.

This thesis investigates a compiler-driven approach to automatically exploit scratchpad memory on UPMEM's DPUs, aiming to simplify programming and achieve performance comparable to hand-optimized code. A novel compilation pipeline is proposed that analyses loops in DMA-unaware C programs and optimizes them into efficient, DMA-aware machine code. The design leverages static analysis, including alias analysis and symbolic analysis, to insert DMA instructions efficiently.

To evaluate the compilation pipeline, the Processing-in-Memory Compiler Benchmarks, based on the Processing-in-Memory Benchmarks proposed by the SAFARI Research Group, are proposed. Experimental results demonstrate significant improvements, achieving an average of 75% of the runtime of hand-optimized programs and sometimes even exceeding the runtimes of the hand-optimized programs.

By automating scratchpad memory management, programmers can focus on high-level functionality while maintaining system performance and compatibility. Future research directions include extending optimizations beyond loops, improving global memory management, and extending the compiler benchmarks with application-based benchmarks.

In this thesis, we present a RISC-V processor that is extended with the MOLEN ISA extension, thereby granting it dynamic reconfiguration capabilities. The reconfigurable microcode (ρμ-code) of the MOLEN paradigm is modified to be suitable for (FPGA) implementation in the 64-bit Linux-capable CVA6 RISC-V processor. The set instruction performs reconfigurations by pointing it to a partial bitstream address, after which the execute instruction can perform operations on the reconfigured hardware. To this end, the concept of nested ρμ-code is presented, in which the reconfigurable opcodes are encapsulated in regular RISC-V instructions. Furthermore, a status instruction is introduced to enable the reconfiguration to be performed in the background. Consequently, the reconfiguration latency can be hidden, by allowing the CPU to do useful work during the reconfiguration. Using various experiments, it is demonstrated that the proposed implementation has a near-optimal reconfiguration performance and that the reconfiguration latency can be effectively hidden in typical cases.

The current trend towards the integration of artificial intelligence (AI) and graphics processing unit (GPU) technologies has resulted in the development of embedded hybrid GPU-AI accelerators, which offer high computational power and energy efficiency. One of the key challenges in designing such accelerators is ensuring their timing correctness, as any timing violation may lead to system failure and incorrect results. To address this challenge, timing simulators have been proposed as a promising solution, as they enable accurate and efficient timing analysis of these complex systems. Nevertheless, such simulators have their limitations: detailed ones, such as cycle-accurate simulators, have high accuracy but exhibit high overhead, while faster approaches, like event-driven simulators, usually cannot achieve high accuracy levels. Therefore, the question arises: How can we implement a timing simulator to achieve a balanced trade-off between accuracy and execution time?

In this context, we introduce NEOX-V, a cutting-edge RISC-V based GPU Processor optimized for GPGPU and AI workloads. However, the current NEOX-V product lacks timing information in its simulator. This has prompted us to use it as a case study to bridge the gap between accuracy and execution time in timing simulators. This is achieved through the implementation of a new feature: a timing simulator that utilizes event-driven modeling.

To assess the proposed simulator's accuracy and effectiveness, we employ a comprehensive validation framework, using diverse workloads and configurations, from simple micro-benchmarks to intricate AI tests. The results demonstrate that the timing simulator achieves an accuracy error below 8\% when compared to the RTL equivalent for all applications, with a marginal increase in actual simulation time of only 0.7\%. It is worth noting that the timing simulator's utility extends beyond predicting execution time; it also plays a crucial role in verifying the existing design and uncovering its limitations.

Overall, this thesis makes a significant contribution to the field of computer architecture by providing a powerful tool for the design, development, and evaluation of an embedded hybrid GPU-AI accelerator called NEOX-V. It is our hope that this work will inspire further research and development in this exciting and rapidly evolving field.

RISC-V is an open-source Instruction Set Architecture that offers a simple, modular, and scalable design. Its extensions allow for customization and optimization based on specific execution workloads. One of these workloads could be quantum computing, which exploits the concepts of superposition and entanglement to manipulate qubits and perform computations that would be infeasible for classical computers. The customization offered by RISC-V presents a remarkable opportunity to develop specialized architectures that can efficiently address the execution of quantum algorithms, bridging the gap between classical and quantum computation.
In this thesis work, a RISC-V 32-bit instruction set extension called qRV32 is developed to address the control of diamond qubits, based on an existing QISA. The architecture defines the encoding syntax for the machine-level instructions and the exchange protocol for control and data in the system. Accordingly to this specification, the hardware of a control core processing the ISE has been designed. Custom functional units and necessary peripherals have been added to the base core CV32E40P in order to implement the desired control functionalities. The thesis also proposed additional work to ease the complete design and functionality of the system. In particular, an assembler targeting qRV32 has been developed, enabling the automated translation of assembly instructions to machine-level code. Furthermore, an experimental model is developed to evaluate the parallelism of the system.
The resulting architecture is eventually tested and evaluated. Software simulations are used to test the functionality of the control core and the custom components. Eventually, a simplified version of the model is used to estimate the parallelism of the core, which can control 23605 network nodes when operating at fclk = 55MHz.

Nowadays, the society strongly depends on computer networks and systems as a means of reliable communication and data storage. In order to maintain absolute security of the networks and thus the society, one would need to separate everything, but this is not feasible. Consequently, sharing of resources is inevitable. There are security products that rely on an FPGA to create domain separation. The domain separation is required to prevent leakage of confidential information and manipulating of critical processes. A modern FPGA has enough resources to have multiple soft-cores initiated on it- each of them working in a different domain. However, due to the limited amount of IO pins on an FPGA, using multiple DRAM chips is not an option. Therefore a single DRAM is shared between multiple soft-cores, threatening the domain separation. The main threats when using a shared DRAM are communication channels due to latency deviations, data corruption due to rowhammering and direct access to unauthorized data due to the data being available on shared addresses. Research has been done to determine what causes the latency deviation and how to mitigate it. The results of the research are that the only fundamental solution to mitigate the latency deviation is to have a fixed latency when accessing the DRAM. A fixed time arbiter is designed and tested. The fixed time arbiter is using a deterministic delay after each DRAM access in order to mitigate the latency deviation. Before mitigating the rowhammer vulnerability it is shown that rowhammering causes bitflips not only in the adjacent rows, but also in non-adjacent rows. To mitigate the rowhammer vulnerability for adjacent rows, a row refresher is created that tracks the rows that are accessed and refreshes the adjacent rows when accessed more than the bitflip threshold. To mitigate the vulnerability for non adjacent rows a test is created to give an overview of all non adjacent rows that contain bitflips so that those rows can be be dedicated as unused guard rows. The last part that is implemented is an address mapper to be sure that no soft-core can access the addresses of another soft-core. The fixed time arbiter, row refresher and address mapper are combined into the memory domain protector. The consequence on the bandwidth of the DRAM is that the bandwidth is halved compared to the benchmark design. The memory domain protector also uses 23× more logic than a standard arbiter. 

Quantum computing is a promising means of satisfying the ever-increasing need for more and faster computations. While some specific applications can already benefit from quantum computing today, a large-scale general-purpose quantum computer is yet to be developed. Many different technologies are being explored to reach this goal, color centers in diamond being a promising candidate. This thesis focuses on a specific kind of color center: the nitrogen-vacancy center (NV center).
Building on top of existing work, a quantum instruction set architecture (QISA) for a quantum computer based on NV centers is designed. A compiler targeting this QISA is designed and implemented using the OpenQL framework. In this process alternative approaches are also explored and contributions useful outside the context of NV centers are made. The final compiler is able to take a quantum circuit operating on logical qubits and transform it into a sequence of QISA instructions operating on physical qubits. This functionality integrates seamlessly with the existing passes in OpenQL, allowing for further extension and the possibility to make use of future developments.
Additional functionality includes optimization, scheduling, and hardware-oriented features such as quantization of operands. Each step is easily configurable using a multitude of scripts and data files, and additional steps can be added in the future if needed.
The functionality of the developed compiler is demonstrated by compiling several circuits, some of which are validated by passing their output through a simulator.
The compiler configuration as used in these tests is able to transform logical circuit into simple physical circuits, but the compiler provides all the functionality to use more complicated logical qubits which incorporate quantum error correction.

Due to recent developments in DNA sequencing technology, there is a growing abundance of available genomic data. To process this information for use in fields such as healthcare and forensics, raw sequencing data have to be processed using computationally intensive algorithms. Currently, one of the major bottlenecks in this processing pipeline is the alignment step, which makes use of dynamic-programming algorithms. To reduce computation times, numerous solutions have been proposed aimed at reducing the execution time of the alignment step. This is done either by accelerating alignment itself using hardware accelerators and heuristics or by reducing the amount of input data through the use of pre-alignment filters. The algorithms associated with the latter solution are less computationally intensive than DP-based alignment, which reduces the end-to-end alignment time.

Currently, pre-alignment filters are effective to the point where the alignment bottleneck is shifted to the filtering step. Therefore, the filters are accelerated on hardware solutions such as GPUs and FPGAs. While these solutions show orders of magnitude improvement in execution times, they are insufficient for removing the filtering bottleneck entirely. The performance of these hardware accelerators is limited by the rate at which data can be supplied. As a solution, we propose a CIM-based accelerator to reduce data-movement overheads between the host device and the accelerator. Additionally, this architecture makes use of emerging non-volatile memories to perform Boolean operations directly within its memory elements. In doing so, it can exploit parallelism in the algorithms to achieve higher throughput.

In this work, we explore commonly found operations in existing pre-alignment filters and devise ways to implement them on the CIM-architecture. The proposed architecture is flexible in supporting multiple pre-alignment filters and a wide range of input data. The functionality of the architecture is verified through simulation and its effectiveness is tested using real data sets.

Using this architecture, we can achieve improvement in end-to-end execution time over the state of the art ranging from 7.2x to 119.6x for the evaluated data sets, while also achieving a reduction of up to 59% and 79.7% in chip-area and power consumption, respectively.

Furthermore, the provided work offers a platform for the development of future pre-alignment filtering algorithms to further improve performance.

Input qubit control signals from an arbitrary waveform generator (AWG) operating at room temperature undergo linear dynamical distortions as it traverses various electrical components on the control line connecting to the quantum device.
If uncompensated for, such distortions can have detrimental effects on gate performance, affecting fidelity and even repeatability. Distortions introduced by components at room temperature (e.g., AWG bandwidth, high-pass filtering of a bias tee, and skin effect in instrumentation cable) are easily characterized using a fast oscilloscope. However, distortions introduced by components inside the refrigerator (e.g., low-pass filters, impedance mismatch, skin effect in semi-rigid coaxial cable, and chip packaging) are generally temperature-dependent and are thus best characterized in the cold. Additionally, the on-chip response varies across devices and even between different qubits on the very same device. Evidently, the ideal strategy for characterizing pulse distortion is to use the controlled qubit itself.
The aim of the thesis project is to implement the various, available protocols for the characterization of control pulse distortions on a superconducting quantum hardware and evaluate their individual performances.

This thesis delves into reconfigurable computing architecture (RCA) design based on emerging embedded non-volatile memory (eNVM) technologies. Traditional Field-Programmable Gate Arrays, while efficient, face inherent limitations when it comes to power consumption and reconfigurability, primarily due to their set amount of resources and reliance on SRAM cells. Emerging eNVM technologies, such as STT-MTJ, ReRAM, and FeFET, offer potential alternatives, each with unique benefits and drawbacks. In this research, we introduce a novel RCA architecture built upon FeFET eNVM technology, which we called the 'Unified Tile'. This architecture is distinctive for its 2D layout of homogeneous tiles, these tiles integrate the three primary functions of an RCA: memory, interconnect, and logic. Our proposed design emphasizes the potential advantages of eNVM technologies over conventional SRAM-based FPGA components.

To validate our design, we employ an event-based simulator developed on the SystemC framework. Through evaluations and benchmarks, our 'Unified Tile' demonstrated notable improvements in power, area, and delay metrics compared to traditional FPGAs. Moreover, when compared with other state-of-the-art eNVM-based RCAs, our architecture showcased competitive, performance. These findings underscore the potential of eNVM-based RCAs as a viable alternative to SRAM-based FPGAs. This research shows the potential of eNVM technologies in reconfigurable computing architectures, with an emphasis on a FeFET-based design. It has also highlighted areas of concern, especially in programming latency, for these emerging technologies.

Highly accurate time sources, such as Cesium-based or GPS clocks, are the best candidates to provide a correct notion of time, but are too costly and impractical for implementation in every modern digital device. Ubiquitously, (crystal) oscillators are employed instead. To maintain a shared notion of time, the offsets and drift/jitter have to be compensated via the concept of synchronization, divided into time offset equalization and syntonization. Packet-based distribution protocols such as Network Time Protocol (NTP) and Precision Time Protocol (PTP) can provide time offset equalization, whilst synchronous Ethernet can deliver syntonization. To reach high synchronization accuracy, PTP and synchronous Ethernet can be combined into an improved protocol, referred to as White Rabbit. It enhances the one-way delay calculation through fine and coarse delay measurements. These improve PTP timestamps to reach sub-nanosecond synchronization accuracy.

The White Rabbit project has limitations though: it relies on extensive calibration parameter sets that are only available for limited devices and do not account for hardware variability. This is in contrast with the initial project objectives. Secondly, the update cycle of the hardware implementation is slow. Namely, the current White Rabbit switch is based on FPGA platforms from ten years ago. Thirdly, the switch contains costly components and requires full replacement of present network switches upon deployment.

This work opted to define a new switch design, which distributes the synchronization tasks over several smaller FPGAs to provide a low-cost implementation and improve applicability, whilst requiring minimal factory calibration and maintaining sub-nanosecond accuracy between devices.

The new switch concept is based on the smaller and widely applied White Rabbit node design. The proof of concept is based on two interconnected FPGAs forming a 1-port White Rabbit switch. Fine delay measurements, asymmetry estimations and fine delay compensations are applied to reach synchronization between the FPGAs. The Digital Dual Mixer Time Difference (DDMTD) is preferred for the fine delay measurements due to its superior resolution, area and invariance to large clock periods. A three-line asymmetry calculation is introduced and motivated to provide an improved one-way delay estimation. Lastly, the IDELAY element was selected to provide the fine delay compensation due to its process-voltage-temperature (PVT) invariance, negligible jitter addition and area demands.

Whilst both the fine delay measurement and fine delay compensation were thoroughly discussed by means of specifications and simulations, the three-line asymmetry calculation had to rely on a theoretical discussion. As such, measurements have shown that the transmission delay over an added bi-directional link is approximately equal when the clock signal moves from slave to master and vice versa. A large delay variability between other transmission lines is subsequently exposed. The variability leads to inaccurate one-way estimations with a traditional two-line approach. A three-line asymmetry calculation will be conclusively beneficial for the synchronization accuracy. The low-cost requirement of the distributed switch can be maintained through elimination of components in the slave and master node. The reduced switch lowers the hardware costs with approximately 25% by trading off cost-effectiveness with jitter filtering and consecutive performance.

The prosperity of the Internet-of-Things (IoT) imposes increasing demand on endpoint microcontroller-based devices' performance and energy efficiency. The MCUs are demanded to process the raw data acquired from the sensors with the integer-based workload, such as digital signal processing (DSP) algorithms and quantized neural network (QNN) inference. Snitch is a tiny RV32I control core based on RISC-V open-source instruction set architecture. Currently, the Snitch system built around the Snitch core aims to achieve high performance in floating-point applications. Novel hardware extensions have been implemented in its floating-point subsystem to achieve high floating-point unit (FPU) utilization, such as stream semantic registers (SSRs) and floating-point repetition (FREP) hardware loop. However, it only has RV32IM instruction set support for integer computation, which does not satisfy the increasing demand from the integer workload we mentioned. In this work, we present a unified Snitch architecture with integer extensions targeting integer workload acceleration. Some existing custom extensions to address performance bottlenecks in DSP and QNN applications were proposed, which are Xpulpimg ISA and sub-byte single-instruction-multiple-data (SIMD) ISA, respectively. Both extensions are built on the outdated version of Snitch in another many-core system Mempool. In our work, we first integrated the DSP-oriented ISA extension Xpulpimg and the sub-byte SIMD ISA extension into the mainline Snitch. Then we extended the existing floating-point SSR to have integer support. To evaluate the proposed extensions, we benchmarked the Snitch core complex (CC) with integer matrix multiplication algorithms and compared the performance between the baseline RV32IM and our extensions. A speedup of 5.9$\times$, 22.6$\times$, and 77.4$\times$ in terms of MACs/cycle with respect to the baseline was measured for 32-bit, 8-bit and 4-bit data sizes, respectively. Post-synthesis figures have been obtained from GlobalFoundries 22 nm technology for area and timing evaluations. Our integer extensions only introduced 12\% area overhead compared with the original FP-capable Snitch CC, and they led to no measurable impact in terms of the maximum effective frequency with FP extensions enabled.

Information exchange through the countless webservices is central in the current age of technology, which increases the importance for security in these developments. One such security feature is the validation of data based on standardized data structures. The aim of this thesis is to develop a flexible hardware-accelerated text-based recognizer that provides this strict syntax validation.

To this end, a parsing machine architecture was adopted in order to fulfill the flexibility and strict recognition requirements. The parsing machine architecture was developed by formalizing the fundamental PEG expressions and creating a micro-architecture based on these PEG expressions, which led to the specification of the PPEG instruction set architecture. This architecture was then mathematically formalized and a proof for its strict adherence to the formalized PEG behavior was provided. The parsing machine architecture was implemented on an FPGA, a virtualization of the parsing machine was implemented in Python for easy analysis of its behavior, and a PEG compiler and assembler were developed for the PEG-PPEG translation. Finally, a memoization unit was developed as an extension to the parsing machine for an improved parsing throughput.

By running benchmarks for CSV, XML, JSON, and Java files on the PPEG parsing machine implementation, its parsing behavior was analyzed and compared to existing solutions. This showed that the minimum stack sizes depend solely on the size and complexity of the PEG; the percentage of clock cycles spent on jumps in instruction and data memory is substantial, ranging from 18\% and 40\%; the PPEG-compiled binary code size is relatively small compared to other solutions; and the throughput of the PPEG parsing machine is comparable if not better than other solutions running on faster hardware. Finally, the memoization unit was found to benefit large complex grammars more than small grammars.

With the replacements of coal and nuclear plants with renewable energy sources such as Type-3 and Type-4 wind turbines and photovoltaic system, the fault current levels of the electrical power system become lower. This leads to a weakened ability of the commercial distance relays to detect fault currents. Therefore, new fault detection algorithms have been developed based on different approaches with the intention of raising the ability to detect faults under different circumstances. Among them, Stockwell Transform has been proved to be a useful tool to determine the occurrence of faults. This thesis presents an FPGA implementation of one of the newly developed S-Transform-based fault detection system on Zynq device. The conceptual methods of building an IEC communication interface to connect the system to an RTDS are investigated.
The algorithm on hardware is implemented in fixed-point representation, fully parameterized, and fully pipelined with the operation frequency at 100MHz. The final implementation is able to provide the result within 570ns. The hardware implementation of the S-Transform-based fault detection system is tested with simulations proving it can perform identically with the MATLAB model of itself.

The world of quantum computing is still quickly developing and growing as it is searching for the best technology to implement quantum bits. One of these technologies is a diamond-based quantum computer using nitrogen-vacancy (NV) centers. In order to sustain the mentioned growth, the limits of electronics as well as computer engineering need to be explored. Consequently, an Instruction Set Architecture (ISA) defining the functionality of the NV centers must be constructed that, in turn, controls the electronics needed to operate the qubits within the NV
center.


In this thesis, we created a simulator to verify the functionality of the ISA and, more importantly, utilize the simulator to explore the capabilities of a diamond-based quantum computer. The simulator mimics the interaction between components and qubits in a diamond-based quantum computer and maps these interactions onto quantum mechanical instructions, such as qubit rotations. The simulator is implemented by modeling the electronics based on literature and creating interaction between the components using an event scheduler. The event scheduler is part of the NetSquid framework in which this simulator is built. The framework has models implemented to represent qubits and perform operations on qubits as well. The qubit representation model represents the electron and carbon nuclei qubits. The quantum operations are used to perform quantum mechanical operations on the qubits.


The simulator is tested for physical accuracy using single diamond tests from literature, namely magnetic biasing, rabi cycle checking, and charge resonance checks. The simulator returned an accurate value for the Larmor frequency and Rabi frequency meaning that it was close to the expected value. For example, setting the Larmor frequency to 1.72GHz and using the magnetic biasing sequence to determine the Larmor frequency resulted in the same 1.72GHz$value.
After single diamond tests have been performed, the control of multiple diamonds and their qubits is tested using a quantum algorithm, the surface-7 code. The simulator accurately mimics the expected behavior of the noiseless execution of the surface-7 code. The results of the simulator follow the trend of the expected values.


The final product of this thesis is a simulator that can accurately describe the interaction between an ISA and the components of the diamond-based system-architecture in the noiseless case. The simulator provides a setup for a future simulator with noise sources implemented, resulting in a simulator that can be used to determine the limits of electronic properties or to predict the outcome of lab experiments.

Functional ultrasound is by now a well-established technique in the neuroscience community to measure brain activity. However, the transcranial application of functional ultrasound on humans, with the exception of the acoustic windows in the skull, remains a huge challenge because of the properties of the cranial bone the acoustic waves will reflect, refract, attenuate or will cause aberration. Therefore, the signal-to-noise ratio (SNR) of the incoming signal is too low for transcranial functional ultrasound (TCfUS). This thesis tries to overcome the SNR problem of TCfUS with the design of a 64-channel ultrasound acquisition system that is focused on achieving the highest SNR possible. This is achieved by placing the analog front-end (AFE) chips as near to the transducer elements as possible and by oversampling the incoming signal with a factor of 25, a theoretical increase of 15 dB of the signal-to-quantization-noise ratio over the current state-of-the-art is estimated. The proposed design is a receive-only system where the transmission of the ultrasound pulses is carried out by a separate ultrasound system. The design splits the acquisition system into a front-end and a back-end subsystem, where the front-end system is implemented using four AFE58JD48 analog front-end chips from Texas Instruments. From here the data samples are transported over fiber optics to the back-end subsystem, which consists of a VCK190 FPGA board from Xilinx, where the samples are processed and/or transported to a workstation for storage. Because the system organization differentiates from more conventional research ultrasound systems, a trade-off is introduced between processing and throughput, resulting in three processing configurations for the FPGA with each a different focus: raw RF data sampling, real-time processing, and hardware processing. Due to time and resource constraints, no measurements and results are available on the SNR and decimation. However, a theoretical exploration has been done on the expandability of the number of channels which was found to be 192 channels for the VCK190.

This paper presents a preliminary study of the set of trade-offs of UC-Berkley’s RISC-V instruction set architecture experiences, due to its lack of the Scaled Index addressing mode. The strong majority of the popular Instruction Sets such as x86, ARM, MIPS and PowerPC include relatively complex ways to calculate memory addresses (addressing modes). On the other hand, RISC-V notably lacks both the Indexed (LOAD rD,[rA+rB]) and Scaled Indexed (LOAD rD,[rA+rB*4]) addressing modes. This design choice impacts many aspects of the Instruction Set. As there’s no such thing as ‘the absolute best Instruction Set’, these aspects will be taken into account as trade-offs, which designers can use make educated decisions. The trade-offs which this study covers include the program size, implementation complexity and performance. These individual trade-offs will be analyzed at a surface level, intended more to explore the existence of anomalies than to go into depth into each topic due to limited time and resources.

Over the last decade, the recognition of the potential value of augmented reality (AR) and other human-machine interfaces has been growing. These applications are all based on depth sensing technologies. Among various depth sensing technologies, the Time-of-Flight (ToF) approach is emerging as a widely applicable method because it has the potential of reaching much longer distances at higher speed and accuracy, is natively suitable for mobile phones or AR.
One obvious problem is that the dToF system mainly targets the automotive industry or 3D imaging in close range, which means different power, accuracy, and fewer area requirements than mobile phone or AR applications. The application of the dToF system in the mobile phone or AR industry needs to be tested. The data volume is another problem of dToF. Usually, in the read out part, the dToF time-to digital converter (TDC)’s timestamps will all be saved into a histogram. The peak value of the histogram is the detected result. However, in a large pixels scenario, the area cost will be too much for mobile phone or AR applications if the whole histogram for all pixels is saved. Hence, an algorithm that can save histogram partially or find out the peak value without saving histogram is needed.
This thesis proposed two novel algorithms for the dToF system’s read out part and tested three other algorithms’ functions in mobile phone or AR applications. With the Lambertian model and probabilistic theory, a module of the dToF system is built using MATLAB to generate a testing dataset. Besides, introductions to depth-sensing technologies, single-photon avalanche diode (SPAD) sensors, and dToF systems will be given before the core chapters of the thesis.

With the increase in the amount of data being gathered, the need for data processing is also rising. Furthermore, in addition to the proprietary ISAs that have been prevalent, the free and open RISC-V ISA has seen major interest. The modularity of the RISC-V ISA allows it to be extended with many instruction set extensions. One such extension that aids in the processing of large amounts of data is the P-extension, which introduces packed-SIMD instructions. In this thesis, the RISC-V based open-source CVA6 processor is extended to support the SIMD instructions defined by the P-extension. In order to do so, the 332 instructions of the P-extension are divided into subsets based on the type of instructions used by applications that make use of SIMD instructions and the hardware needed to implement those instructions. Due to time constraints 268, or 80.7%, of the total 332 instructions were implemented. However, this includes all the instructions that could be utilized by the used benchmarks. Therefore, the benchmark results show the full performance achievable by the P-extension. These 268 instructions make up the basic, MAC 8-bit, MAC 16-bit, and MAC 32-bit subsets. The ALU has been modified to operate in a SIMD manner on 8 8-bit, 4 16-bit, 2 32-bit, and 64-bit elements. Moreover, it has been extended to support new operations like data movement or reorganization instructions. Like the ALU, the multiplier has also been converted into a SIMD multiplier using a SIMD Baugh-Wooley scheme. Furthermore, the multiplier has been extended to also function as a MAC unit. The impact of these newly added SIMD instructions is tested in an ideal scenario of matrix multiplication as well as in a real-world machine learning application. In matrix multiplication, a speedup of up to 8.8x and 7.2x is seen for 8-bit and Q7 elements and 4.9x and 3.8x for 16-bit and Q15 elements when only using instructions from the basic subset. When also using the MAC instructions, the speedup increases to up to 12.3x and 12.6x for 8-bit and Q7 elements and 6.7x and 6.5x for 16-bit and Q15 elements. The real-world benchmark consists of an image recognition convolutional neural network based on the CIFAR-10 data set. In this benchmark, a speedup of 2.1x and 3.3x is obtained for respectively the basic subset and with MAC instructions. However, the additional hardware comes at a cost, specifically an increase of 5.0% LUT and 0.05% flip-flop usage for the basic subset or 7.2% increased LUT and 0.56% increased flip-flop usage with the basic and MAC subsets. While the additional hardware can have an impact on the maximum achievable clock frequency, the critical path remains in the FPU. The maximum achievable clock frequency is therefore not impacted and reaches 70 MHz on a Xilinx Kintex-7 FPGA.

Nowadays, the need for better and faster computing searches for solutions in the field of quantum computing. It is believed that quantum computing can and will surpass conventional, classical computing. When quantum computing surpasses classical computing, it is called quantum supremacy. There are many different projects that use different quantum technologies aim to achieve quantum supremacy, such as projects from Google and Intel. In this thesis, the reader is introduced to a new project: the Fujitsu Project. The project is a collaboration between TU Delft and Fujitsu and has the goal of fabricating a new distributed quantum quantum computer based on color centers in diamond. The focus of the thesis is the definition of the microarchitecture.

The quantum computer stack is explained in detail. Precise and robust definitions for each of the seven layers of the quantum computer stack are given, where the definition of the microarchitecure is most important. A microarchitecture is defined as the list of instructions of the lowest level before entering control electronics. To define the diamond microarchitecture, a set of goals have to be completed. Other architectures such as QuTech's QuMA and QuTech's Central Controller were identified and analyzed. Combined with the requirements of the overall diamond system architecture as defined by the project, a list of requirements for the microarchitecture is created. Using these requirements, a Quantum Instruction Set Architecture (QISA) and a microarchitecture are defined.

Based on the defined QISA and microarchitecture, a compiler is designed. The compiler is made in OpenQL. OpenQL is a framework for high-level quantum programming that targets different quantum computing platforms. The main task of the compiler is to translate high-level quantum algorithms, expressed in a high-level quantum programming language (C++/Python APIs), to quantum microcode. The quantum microcode consists of instructions that are defined in the microarchitecture.

The QISA, microarchitecture and compiler are verified against the requirements that are set at the beginning of their respective definition phases. The microarchitecture supports for all gates that are part of cQASM 1.0. In addition, it supports all diamond color center specific protocols and rules. The compiler supports all instructions from cQASM as well. Moreover, the compiler supports all standard (gate) instructions and diamond specific instructions through OpenQL's Python API.

The work is intended to be a solid baseline, where the future of the project can rely and improve upon. Possible improvements could be the adaption of the microarchitecture to the growth of the number of controlled qubits per controller, the parallelization of the microarchitecture instructions to improve instruction throughput, and alignment with the quantum network group. The compiler can also be improved with for example enhanced scheduling, differentiation between qubit types and an entanglement library. The next step in the design of the microarchitecture will be the design of a microarchitecture simulator, which takes the microcode as input and simulates the hardware architecture.