This thesis addresses the growing demand for faster and more reliable data transfer solutions in data-intensive applications, with a strong emphasis on scalability and flexibility. The research centers on the design and implementation of a high-speed data transfer system that utilises PCIe over fiber optics. The main objective is to explore how PCIe technology can be effectively extended over long distances using fiber optics, while maintaining high throughput and low latency, essential for supporting the demands of modern data-intensive environments.

The design and implementation of the system were approached methodically, with careful selection of components and a focus on optimising the system architecture for performance. Detailed experimentation was conducted to evaluate the system's capabilities, resulting in successful data transfer rates of up to 58.02 Gbps using a Gen3 x8 PCIe configuration over a 10-meter fiber link. These findings confirm the viability of PCIe over fiber as an effective solution for high-speed data transfer, while also identifying specific areas where further improvements could be made.

Future work could explore the adoption of newer PCIe generations and the optimisation of critical parameters, such as Maximum Payload Size (MPS). Additionally, there is potential to enhance the system's performance by investigating optical connectors capable of supporting sideband signals. These advancements would further improve the system's adaptability and efficiency across a wide range of application scenarios.

In modern High-Performance Computing (HPC) systems based on Field Programmable Gate Arrays (FPGA) accelerators, First-In, First-Out queues (FIFOs) are crucial for data buffering and balancing, particularly in demanding applications requiring high-throughput data streaming. Some prominent examples are: large scale signal processing, machine learning, and online network processing. Typically, these FIFOs are implemented using the available on-chip blocks RAM (BRAM) blocks organized as a circular structure, leveraging the reconfigurable nature of FPGAs to manage data efficiently. However, as applications have to process larger and larger data capacities, the associated area and power consumption of these BRAM based implementations consume significantly large portion of the on-chip resources, posing challenges for both performance and efficiency.

This thesis explores an alternative approach for large and efficient reconfigurable on-chip FIFOs by designing a dedicated ASIC block containing linear shift register structure. Unlike circular FIFOs, which rely on complex control units such as address pointers and decoders, the linear FIFOs simplify the implementation by directly shifting the data through the registers. This approach eliminates the need for the additional intricate control logic typically associated with FPGA circular buffers, making it a potentially more efficient solution for a large class of streaming applications.

The first phase of this work focuses on implementing various FIFO designs on a Xilinx Virtex-7 series FPGA, utilizing different on-chip memory resources: registers, lookup tables (LUTs), and BRAM blocks. These implementations are investigated across different bit widths, in the range of hundreds of bits, and FIFO depths of several thousand stages. The second phase compares these FPGA implementations with an ASIC-based linear FIFO of similar size, synthesized using the TSMC 40 nm standard cell library. The results demonstrate that while the ASIC-based linear FIFO offers over twice the performance of the FPGA-based designs, it requires six to seven times more area. This is attributed to the fact that register-based storage cells are approximately ten times larger than SRAM cells, highlighting the inherent trade-off between performance and area in such designs.

To address the above area overhead, this project further investigates the use of two ring-counters to replace the address decoders typically found in SRAM-based FIFO designs. As data storage requirements increase, the complexity of address decoders also grows. By simplifying the control logic with ring-counters, the design achieved area reductions of 50\% to 76\% for FIFO depths of 1 Kbits and 2 Kbits across various bit widths. These findings underscore the significant potential of this approach to optimize both area and performance in memory-intensive FPGA applications.

Emerging, non-volatile memories are promising solutions to contemporary computing problems. These include In-Memory Computing, Neuromorphic Computing, and Machine Learning. We believe that these are not the only possible applications of non-volatile emerging memory devices and that these can be used effectively for tackling several challenges of the ”conventional” computer architecture. For instance, address decoders are an integral part of random access memories. They are typically implemented using fast logic optimised for low latency. They are, however, difficult to test, while their repair is considered to be impossible. In this thesis we research the possibility of a highly scalable and testable address decoder solution, based on Content-Addressable Memories build with ferroelectric transistors (FeFET). This solution can offer numerous advantages including transistor count close to state of the art designs, while outperforming them in terms of latency. In addition, a key advantage could emerge during the testing of this decoder; due to its regular 2D structure, it’s testability is comparable to that of conventional memory arrays. Moreover, it can enable higher production yields, considering that adding a few spare rows will enable end-of-production repair, in the presence of manufacturing defects. By additionally increasing the number of address bits stored in a single FeFET CAM cell, further potential area reductions of 30% - compared to the traditional dynamic NAND decoders - can be achieved.

With the rise of the artificial intelligence starting in the late 2010s there has been a great increase of demand for neural networks. It seems AI is omnipresent these days, whether it is OpenAI releasing the famous or infamous large language model chatGPT, Google following by adopting a similar approach with integrating Artificial Intelligence (AI) into it's search engine or help desks becoming entirely controlled by AI. It is clear, AI is here to stay. NVIDIA normally a company thought of selling Graphical Processing Units (GPUs) for gaming purposes has shifted its focus to making GPUs used for running neural networks, this shift has shown its returns as it is now the most valuable company in the world.

The increased interest in AI does leave a lot of academia wondering: What actually is artificial intelligence and especially what are neural networks. With the introduction of deep learning, a machine learning method that searches for features in a dataset, neural networks have become more and more abstract. Developing an appropriate solution to better interpret, visualize and adjust the inner workings of a neural network is not just needed to keep track of the underlying dynamics of a neural network, but also to allow the user to go outside of the standardized framework to fine tune a network.

This thesis explores the functionality of neural networks, more specifically spiking neural networks, and describes the workings and functions of the created simulator. Multiple helper functions, that allow the user to both visualize and adjust the network outside of the standardized framework, are introduced that distinguishes the created simulator from the already present SNN simulators. Afterwards, five small simulations are done to validate the basic functionality of the simulator. Following these simulations the simulator is validated using two large datasets and comparing the simulator with the results from a well known spiking neural network library SLAYER. The first validation is done with a smaller data set containing hand written images of the numbers zero to nine. The second validation is done with a larger data set containing multiple different kind of performed hand gestures. Both validations show that the simulator has a high accuracy with the maximum mean square error between the SLAYER output and the simulators output being less than 2%.

The number of wireless devices has grown exponentially in recent years, and Bluetooth is a major component of personal wireless communication devices. In some Renesas Bluetooth devices, a Configurable Media Access Control (CMAC) is responsible for the real-time control of the radio front-end and execution of lower layers of Bluetooth applications and it uses an embedded ARM CPU. However, this design faces limitations in core architecture modification and requires royalty payments.

This thesis investigates the feasibility of replacing the ARM processor with a RISC-V core within the CMAC to overcome these limitations. RISC-V, an open-source instruction set architecture, offers the flexibility of custom instruction extensions that can be used to accelerate Bluetooth applications and a core can be freely implemented without licensing fees. These features make it a promising alternative for the CMAC internal CPU.

This thesis defines a set of Key Performance Indicators (KPIs) relevant to the requirements of the CPU within the CMAC and conducts a comprehensive investigation of RISC-V cores, ranging from open-source to commercial cores. Ultimately, the Renesas' in-house developed RISC-V core is selected as the candidate. Multiple benchmarks are then performed to evaluate its performance. The benchmarks demonstrate that the RISC-V core outperforms the original ARM core by 33% in execution speed while reducing design costs despite a larger gate count. Additionally, the code size gap of the RISC-V implementation can be reduced to 7% through the use of the code size reduction instruction extension (Zc).

Repetitive register field manipulation patterns are identified as a common pattern in CMAC firmware and custom instructions are proposed and simulated to accelerate these patterns. The custom instructions can achieve a maximum of 36,73% in cycle count and 43,84% in code size for targeted benchmarks.

These results suggest that the RISC-V core in CMAC can provide both performance improvement and cost savings compared with the existing ARM design while offering greater flexibility. With custom instructions, the RISC-V processors can be further adapted for specific Bluetooth applications. This thesis offers a guideline for developing future Bluetooth devices with RISC-V processors.

In the rapidly evolving realm of embedded systems, debugging is a critical component in the lifecycle of embedded firmware development, especially given the high demands of performance in real-time systems. Debugging embedded systems is inherently challenging and time-consuming due to limited internal system observability. Many modern processors, specifically those based on the ARM architecture, are equipped with debugging features such as Coresight components and debug registers to aid the debugging process. However, most debugging solutions rely on external hardware, which is often removed or disabled in a production system. Furthermore, existing software/hardware debug platforms do not support co-debug capabilities for multicore and multiprocessor debugging. This research aims to tackle the challenges developers face due to limited resources, strict real-time constraints, and the complex nature of debugging in embedded systems. The focus is on enhancing code efficiency and ensuring system responsiveness within stringent timing constraints. This thesis introduces a software library solution for debugging and profiling firmware, leveraging trace infrastructure and debug registers for multicore and multiprocessor ARM-based SoCs, facilitating comprehensive system analysis across ARM R5, M4, and M33 series processors. The library supports performance measurement, profiling, hardware breakpoints and watchpoints, synchronous breakpoints in multicore systems, and inter-processor communication. Furthermore, integrating Embedded Trace Macrocell and Micro Trace Buffer allows for detailed tracing across all processors, significantly enhancing system observability and debugging efficiency. Notably, the library is designed to be user-friendly, hardware-agnostic, and easily expandable to other ARMv7, and ARMv8 series processors. Comparative results documented in this study highlight the library’s low overhead and latency. This thesis advances technical capabilities in debugging embedded systems and strategically enhances design decisions and process optimizations, ultimately contributing to more robust and efficient embedded solutions.

Internet of Things (IoT) devices regularly process sensitive data, including personal information. Therefore, ensuring their security is crucial to avoid damage and prevent data breaches. The Advanced Encryption Standard (AES) is generally regarded as one of the most popular cryptographic algorithms for ensuring data security. Typical lightweight implementations of the algorithm published in the literature focus on area and power optimization, while neglecting the performance. This paper presents a novel lightweight approach for the AES algorithm and considers both encryption and decryption. In terms of performance per unit area and performance per unit power, our 32-bit design outperforms the state-of-the-art by 1.69x and 1.27x, respectively. These improvements become even larger when implementing higher data-path designs, such as 64-bit or 128-bit designs. Our non-DOM AES design is secure against Correlation Power Analysis (CPA) but vulnerable to Template Based Attack (TBA) when more than 1500 traces are considered. To enhance its resilience against side channel attacks (SCAs), we modified our design by adopting and further improving on the most recent countermeasure, i.e., Domain-Oriented Masking (DOM). The results demonstrate that incorporating DOM into our design enables it to withstand against both CPA and TBA. Besides, our simplified eight-stage and five-stage 1st-order DOM SBOX designs achieve a reduction in area of 9.9% and 6.9% compared to the original proposed designs, respectively.

Rowhammer is a security exploit used to cause bit errors DRAM chips. Newer DRAM technologies are becoming more vulnerable to rowhammer attacks, and existing protec- tion methods are starting to reach their limits. This thesis provides methods for DRAM characterization by means of reverse engineering, an in-depth analysis of vulnerable cells during rowhammer and a novel protection method. First the DRAM module is characterized by performing a retention test and a one- sided rowhammer attack throughout the memory. The resilience to rowhammer of vul- nerable victim cells has been analysed by using various data patterns in the victim cell itself in combination with its direct and diagonal neighbours. The impact of the pro- posed protection method is measured by flipping the data in the attacker row during a simulated rowhammer attack. Various rowhammer sequences are investigated. The results following the DRAM characterization show that only a one-sided rowham- mer attack is possible. Rows that impact one another during rowhammer come in pairs of two, one attacker row impacts only one neighbouring row. The results of the in-depth analysis of cells during rowhammer shows evidence of negative horizontal impact com- ing from uncharged neighbouring cells in the same row and negative diagonal impact coming from charged cells neighbouring the attacker cell in the attacker row. The hori- zontal impact is mirrored in symmetrical cells whilst the diagonal impact is not. Results following the proposed protection method experiments show that using the protection method improves the overall resilience to rowhammer ranging from 50%, 65% to 100% depending on the hammer sequence.

Computer Architects often walk the tightrope between performance, power and area while designing modern day processors. This daunting task is made even more challenging by short Time-to-Market requirements set by the clients. In light of these challenges, architectural simulators provide a much needed tool for the architects to gauge the impact of their innovations rather quickly. Arguably, use of such simulators is essential in avoiding a product recall due to the processor failing to deliver on performance/power requirements for the intended application. The thesis is in-line with the objective of identifying and addressing the bottlenecks in the RISC-V simulation ecosystem and contribute in the development of RISC-V infrastructure.
The intended objective of an architectural simulator is to capture the trend of the real hardware (i.e., performance improvement due to micro-architectural changes in real hardware should be eloquently captured by the simulator). A good simulator shall have high throughput (less simulation time) and should be easily re-configurable. The re-configurability of the simulator can be as fine as micro-architectural changes or as large as a new ISA being simulated. These attributes of speed and re-configurability come at the cost of accuracy. A high error in performance statistics of the simulator fails to engender confidence among the prospective users. Hence, validating performance of simulators against hardware is essential.
The thesis introduces the need for a full system architectural simulator for RISC-V processors followed by a brief, yet crisp review of the past attempts at making such simulators. The review is from the perspective of existing methodologies for performance validation of the simulators. The work also proposes a new methodology for validating system simulators. Although, the proposed methodology is generic and can be extended to other ISAs (such as ARM, x86, etc.), the target hardware chosen are RISC-V ISA based systems that span both commercially, IP protected processor as well as open-source processors widely adopted by the RISC-V community.
The error in validated simulator is reduced to 22.9% and 18.9% for selected SPEC2017 benchmarks applications, by calibrating the CPU model. The methodology also streamlines CPU performance validation of the simulators.

Over the last decade, applications like self-driving, image recognition and speech processing are having more and more impact on the society, all these applications are based on machine learning, and machine learning is all about metrics and vectors. For that reason, vector processors are getting attraction again.

Most of the previous research of vector processor focuses on single-core performance, and most of today’s large-scale computer system use non-uniform memory access (NUMA) architecture, how to efficiently deploy the vector processor in a NUMA environment remains a problem. NUMA is a shared memory model, with a NUMA system, there are multiple memories distributed in the system and usually each NUMA node has one memory. It will take the processors longer to access memories in other nodes then the memory in the same node, and this feature shows some opportunities to increase the performance of the NUMA system by accelerating the remote memory accesses.

In this thesis, a subset of the PARSEC benchmark are vectorized for both ARM Scalable Vector Instructions (SVE) and RISC-V Vector Instructions (RVV), and the single-core performance of these two types of processors will be compared based on this benchmark. Then a NUMA system is made for ARM SVE and the memory access pattern is analysed with gem5 simulator.

Manufacturers of CubeSats prefer the use of COTS electronic components such as microcontrollers (MCU) and SDRAM but these components are vulnerable to errors caused by radiation. A specific type of error caused by radiation are soft errors which can be corrected by Error Detection and Correction (EDAC) methods. Unfortunately, it is uncommon for MCUs to have an (optimal) EDAC solution integrated in their memory controller. In these cases an external solution is required.
This work proposes a generic methodology towards transparent FPGA-based correction of soft errors that can be applied given a specific microcontroller and its off-chip main memory. To determine how powerful the EDAC solution must be the methodology uses reliability models to evaluate the MTTF of the memory system. Then, the methodology describes how the EDAC logic must be designed in the FPGA fabric such that the FPGA and its EDAC logic are transparent to the MCU. A method to periodically scrub the memory transparently to the processor is also included.
A major trade-off of the FPGA based design is that it requires the clock of the MCU memory controller to be lowered to meet the timing requirements of the SDRAM interface. For some designs it is also necessary to lower the memory capacity or to use more SDRAM devices to store the ECC parity bits.
Lastly, a hardware demonstrator was built to provide EDAC capabilities to the onboard computer developed by ISISPACE. The design consisting of an ARM9 microcontroller, an FPGA and two SDRAM devices is capable of correcting a single error in each byte of the 32- bit SDRAM interface of the MCU and can scrub the entire memory in 33 seconds. Software benchmarks showed that computing performance is about half of the original board as a result of halving the memory controller clock.

Over the last decade, the recognition of the potential value of augmented reality (AR) and other human-machine interfaces has been growing. These applications are all based on depth sensing technologies. Among various depth sensing technologies, the Time-of-Flight (ToF) approach is emerging as a widely applicable method because it has the potential of reaching much longer distances at higher speed and accuracy, is natively suitable for mobile phones or AR.
One obvious problem is that the dToF system mainly targets the automotive industry or 3D imaging in close range, which means different power, accuracy, and fewer area requirements than mobile phone or AR applications. The application of the dToF system in the mobile phone or AR industry needs to be tested. The data volume is another problem of dToF. Usually, in the read out part, the dToF time-to digital converter (TDC)’s timestamps will all be saved into a histogram. The peak value of the histogram is the detected result. However, in a large pixels scenario, the area cost will be too much for mobile phone or AR applications if the whole histogram for all pixels is saved. Hence, an algorithm that can save histogram partially or find out the peak value without saving histogram is needed.
This thesis proposed two novel algorithms for the dToF system’s read out part and tested three other algorithms’ functions in mobile phone or AR applications. With the Lambertian model and probabilistic theory, a module of the dToF system is built using MATLAB to generate a testing dataset. Besides, introductions to depth-sensing technologies, single-photon avalanche diode (SPAD) sensors, and dToF systems will be given before the core chapters of the thesis.

Many devices currently connect to the internet. Some are pretty well secured, while others lack security due to bugs or other vulnerabilities. A scanner searches for available services on the internet or computer host using standard network protocols. An adversary uses a scanner to search for leaks in security. However, scanners encode their network traffic with a specific XOR pattern, also called a fingerprint of the scanner. However, finding those patterns is very computation-intensive on classical hardware. This thesis aims to use a special FPGA, namely a DFE, to find the fingerprints at a higher speed of 10 GBits/s. Additionally, it aims to find the limits of this DFE in terms of computation power and speed. We created a performance model to find the design requirements and used this data to choose the most optimal algorithm to find the fingerprints. The performance model showed that we would not reach the intended 10 GBits/s speed. Therefore, we chose the solution that would bring us as close as possible. The potential bandwidth we could reach is 2.4 GBits/s, approximately 12.7 times faster than an optimal high-end CPU implementation using a Ryzen Threadripper 3990x CPU.

The field of Computing has been a significant catalyst for innovation across various segments of our lives. Computational neuroscience keeps demanding increased perfor- mance to implement powerful simulators able to closely approximate brain behavior using complex mathematical models. This resulted in various High-Performance Com- puting systems able accelerate the above simulation workloads. One of the challenges is how these applications are being ported to massively parallel accelerators that requires significant time and effort for designing and debugging. This thesis primary task is to optimize an existing hardware library for neural simulation. The above library uses one of the most widely used biophysically-meaningful neuron models called Hodgkin-Huxley. The library optimizations will be performed while following a design methodology to accelerate applications on Maxeler’s Data-Flow Engines (DFEs). A DFE is an FPGA- based accelerator incorporating a top-of-the-line reconfigurable device surrounded by high bandwidth, large capacity on-card memory. This work focused in the fully ex- tended model that had room for performance improvements. The result, an optimized model that takes advantage of the FPGA capabilities and achieve up to 2.66x speed up over the previous implementation. They key to this speedup is the use of fixed-point arithmetic that provides 2x speed up compared to the optimized floating-point version. Additionally, the model is implemented in multiple kernels in such a way that can be scaled up using multiple DFEs to achieve even greater performance.

In an effort to make DNA sequencing more accessible and affordable, Oxford Nanopore Technologies developed the MinION: A portable cellphone sized DNA sequencing device. Translating the information from this device to a nucleotide sequence is called basecalling, and is done with the aid of artificial neural networks. In this thesis, we accelerate a neural network using the concept of Dataflow programming. The result is a complete basecalling application that relies on an FPGA based platform to run the compute intensive parts. We achieve up to 1.51x speedup over a high-end server with two Intel Xeon Processors, with a rate of 57,040 bases per second. In addition, our implementation uses up to 90.27\% less energy compared to the original implementation.

The increasing transistor density of Integrated Circuits (ICs) ever since their introduction, has scaled the computational performance of microprocessors. As a consequence of the gain in transistor density, the power dissipation density has also increased to a degree that has become a limiting factor in further performance scaling. The prevalent control flow computing paradigm is, especially in the context of High Performance Computing (HPC), faced with this power crisis. Data flow computing can achieve a better computations per unit power ratio and might therefore be the solution to achieving exa-scale computing, enabling progress in science and technology.
This work contributes in investigating methods for increasing the abstraction
level of data flow programming by using a Polyhedral Process Network (PPN) as abstraction to facilitate automated analysis and transformation of data flow applications. A Polyhedral Process Network (PPN) is a process network based on Polyhedral Compilation (PC) a mathematical framework for code analysis and optimisations.
A tool has been implemented to translate a PPN to a data flow implementation. The Maxeler Data Flow Engine (DFE) technology, a data flow hardware platform supported by a tool-flow, is used as target technology. For a number of specific challenges involved in the transformation from PPN to DFE-implementation a method has been implemented. This has shown that a PPN as well as the capabilities of PC are useful concepts that are applicable to further increase of the abstraction-level of data flow computing. However the transformation from PPN to DFE-implementation is complex. Therefore this work concludes that the development of a data flow tailored Polyhedral Compilation (PC) abstraction is the most promising future direction.

The finite element method (FEM) is an ubiquitous method for the analysis of boundary value problems. Specifically, it can be used to find approximations to solutions of boundary value problems on a specific domain...