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Mohamed A. Bamakhrama

3 records found

Authored

Rapid Design-Space Exploration for Low-Power Manycores under Process Variation utilizing Machine Learning

Journal article (2022) - Sohaib Majzoub, Resve A. Saleh, M. Taouil, S. Hamdioui, Mohamed A. Bamakhrama

Design-space exploration for low-power manycore design is a daunting and time-consuming task which requires some complex tools and frameworks to achieve. In the presence of process variation, the problem becomes even more challenging, especially the time associated with trial-and-error selection of the proper options in the tools to obtain the optimal power dissipation. The key contribution of this work is the novel use of machine learning to speed up the design process by embedding the tool expertise needed for low power design-space exploration for manycores into a trained neural network. To enable this, we first generate a large volume of data for 36000 benchmark applications by running them under all possible configurations to find the optimal one in terms of power. This is done using our own tool called LVSiM, a holistic manycore optimization program including process variations. A neural network is trained with this information to build in the expertise. A second contribution of this work is to define a new set of features, relevant to power and performance optimization, when training the neural network. At design time, the trained neural network is used to select the proper options on behalf of the user based on the features of any new application. However, one problem encountered with this approach is that the database constructed for machine learning has many outliers due to randomness associated with process variation which creates a major headache for classification - the supervised learning task performed by neural networks. The third key contribution of this work is a novel data coercion algorithm used as a corrective measure to handle the outliers. The proposed data coercion scheme produces results that are within 3.9% of the optimal power consumption compared to 7% without data coercion. Furthermore, the proposed method is about an order of magnitude faster than a heuristic approach and two orders of magnitude faster than a brute-force approach for design-space exploration.@en

Parallelization of variable rate decompression through metadata

Conference paper (2020) - Lennart Noordsij, Steven Van Der Vlugt, Mohamed A. Bamakhrama, Mohamed A. Bamakhrama, Z. Al-Ars, Peter Lindstrom

Data movement has long been identified as the biggest challenge facing modern computer systems' designers. To tackle this challenge, many novel data compression algorithms have been developed. Often variable rate compression algorithms are favored over fixed rate. However, var ...

Contributed

Evaluation of RISC-V for Software-defined Medium Access Control

Master thesis (2024) - S. Xu, G. Gaydadjiev, Mohamed A. Bamakhrama, C. Gao

The number of wireless devices has grown exponentially in recent years, and Bluetooth is a major component of personal wireless communication devices. In some Renesas Bluetooth devices, a Configurable Media Access Control (CMAC) is responsible for the real-time control of the radio front-end and execution of lower layers of Bluetooth applications and it uses an embedded ARM CPU. However, this design faces limitations in core architecture modification and requires royalty payments.

This thesis investigates the feasibility of replacing the ARM processor with a RISC-V core within the CMAC to overcome these limitations. RISC-V, an open-source instruction set architecture, offers the flexibility of custom instruction extensions that can be used to accelerate Bluetooth applications and a core can be freely implemented without licensing fees. These features make it a promising alternative for the CMAC internal CPU.

This thesis defines a set of Key Performance Indicators (KPIs) relevant to the requirements of the CPU within the CMAC and conducts a comprehensive investigation of RISC-V cores, ranging from open-source to commercial cores. Ultimately, the Renesas' in-house developed RISC-V core is selected as the candidate. Multiple benchmarks are then performed to evaluate its performance. The benchmarks demonstrate that the RISC-V core outperforms the original ARM core by 33% in execution speed while reducing design costs despite a larger gate count. Additionally, the code size gap of the RISC-V implementation can be reduced to 7% through the use of the code size reduction instruction extension (Zc).

Repetitive register field manipulation patterns are identified as a common pattern in CMAC firmware and custom instructions are proposed and simulated to accelerate these patterns. The custom instructions can achieve a maximum of 36,73% in cycle count and 43,84% in code size for targeted benchmarks.

These results suggest that the RISC-V core in CMAC can provide both performance improvement and cost savings compared with the existing ARM design while offering greater flexibility. With custom instructions, the RISC-V processors can be further adapted for specific Bluetooth applications. This thesis offers a guideline for developing future Bluetooth devices with RISC-V processors.