As the use of Internet-of-Things (IoT) devices in medical treatment and health moni toring continues to expand, traditional battery-powered sensors are becoming increas ingly inadequateduetothechallengesassociatedwithbatteryreplacement,whichoften necessitates additional surgeries and medical care. In contrast, thermoelectric energy harvesting (TEH) systems, which convert ambient thermal energy into electrical energy, offer a sustainable solution for wearable devices. TEH systems, known for their high energy density and flexibility, have the potential to make IoT devices self-powered by utilizing ambient thermalenergy. However,itisdifficulttoefficiently extract powerfrom low-temperature gradients. Previous studies have only achieved high energy-harvesting efficiency within limited ranges of thermoelectric generator (TEG) voltage (VTEG) and TEG internal resistance (RTEG). This limitation arises due to the high power consump tion of control systems, which consume a significant portion of the harvested energy, particularly under low VTEG and high RTEG conditions. To address these challenges, an interface for TEH systems with ultra-low power consumption and precise control mod ules is urgently needed. This project is divided into two parts. The first part involves summarizing and com paring the state-of-the-art in TEH, with a focus on advanced techniques used in other TEH systems and the potential for ultra-low power consumption. The remainder of the thesis proposes an all-digital controlled TEH interface that incorporates SAR zero current sensing (ZCS) and digital Maximum Power Point Tracking (MPPT). Theoretical analysis, designdetails, andmeasuredperformanceofthissystem—thefirstfullydigital controlled TEHsystem—arethoroughlydiscussed. Thechiphasalreadybeenfabricated andtested

Unmanned aerial vehicles (UAVs), often referred to as autonomous drones, are becoming more and more prevalent in our daily lives. Drones are usually equipped with traditional frame-based cameras and have functions like object detection. However, the high energy consumption of frame-based cameras presents a challenge to drone endurance. In addition, due to its own hardware limitations, problems such as blurring and deformation will occur when capturing high-speed moving objects. In contrast, event cameras, as one of the latest neural technology cameras, have the characteristics of low power consumption, low latency, and sensitivity to high-speed objects. This makes them well-suited for integration into drone platforms. In this thesis, we introduce a method for high-speed moving object recognition based on event cameras. This approach involves enhancing objects with externally added ``common features": fiducial markers, and employing a custom-developed deep learning neural network to detect these markers. These marks can carry some messages, such as the information of related objects. When these marks are detected, it is considered that objects are detected. We also developed a fiducial marker decoding method based on region segmentation to obtain the message content, thereby achieving interaction with the detected object. Evaluation results show that the proposed method has a low computing time of 26.9 ms, low storage and memory usages of 670 MB CPU memory and 750 MB GPU video memory, and a high accuracy of 77.9%, making it suitable for high-speed object recognition based on event cameras.

The number of wireless devices has grown exponentially in recent years, and Bluetooth is a major component of personal wireless communication devices. In some Renesas Bluetooth devices, a Configurable Media Access Control (CMAC) is responsible for the real-time control of the radio front-end and execution of lower layers of Bluetooth applications and it uses an embedded ARM CPU. However, this design faces limitations in core architecture modification and requires royalty payments.

This thesis investigates the feasibility of replacing the ARM processor with a RISC-V core within the CMAC to overcome these limitations. RISC-V, an open-source instruction set architecture, offers the flexibility of custom instruction extensions that can be used to accelerate Bluetooth applications and a core can be freely implemented without licensing fees. These features make it a promising alternative for the CMAC internal CPU.

This thesis defines a set of Key Performance Indicators (KPIs) relevant to the requirements of the CPU within the CMAC and conducts a comprehensive investigation of RISC-V cores, ranging from open-source to commercial cores. Ultimately, the Renesas' in-house developed RISC-V core is selected as the candidate. Multiple benchmarks are then performed to evaluate its performance. The benchmarks demonstrate that the RISC-V core outperforms the original ARM core by 33% in execution speed while reducing design costs despite a larger gate count. Additionally, the code size gap of the RISC-V implementation can be reduced to 7% through the use of the code size reduction instruction extension (Zc).

Repetitive register field manipulation patterns are identified as a common pattern in CMAC firmware and custom instructions are proposed and simulated to accelerate these patterns. The custom instructions can achieve a maximum of 36,73% in cycle count and 43,84% in code size for targeted benchmarks.

These results suggest that the RISC-V core in CMAC can provide both performance improvement and cost savings compared with the existing ARM design while offering greater flexibility. With custom instructions, the RISC-V processors can be further adapted for specific Bluetooth applications. This thesis offers a guideline for developing future Bluetooth devices with RISC-V processors.

Piezoelectric (PE) and electromagnetic (EM) methods are two popular techniques for harvesting kinetic vibration energy. When combined, these methods can power self-sustaining wireless sensors that require higher power consumption. However, existing hybrid energy systems necessitate at least one large off-chip inductor for either bias-flip or DC-DC conversion. This large inductor significantly increases the system's volume, leading to integration issues in space-constrained Internet-of-Things (IoT) applications.
This thesis proposes a fully integrated PE-EM hybrid energy harvesting platform to address this issue. By properly arranging synchronous PE and EM phases, the new active-to-passive coil-sharing technique eliminates the need for an additional energy reservoir for bias-flip and DC-DC. The IC prototype, fabricated using the 0.18um BCD CMOS process, has been experimentally tested. Results show a flipping efficiency of up to 70%. Additionally, the proposed single-stage system structure allows the output to be parallel with the battery stage, achieving high end-to-end (E2E) efficiency.

This thesis presents the process of design and implementation of a power grid simulator, with focus on the power grid configuration and load forecasting as part of a larger project. The overarching project aims to address the increasing complexity of power grids and the occurence of grid congestion. Its primary objective is to visualize these issues for educational purposes. For this subsystem, the specific goal is to provide a grid configuration, all necessary data to simulate it, and load predictions for the grid.

The automotive industry is experiencing a significant shift towards advanced electronic and software integration, driven by the increasing demand for self-driving and autonomous vehicles. With electronics now making up a major portion of vehicle costs, ensuring their reliable operation is critical. However, as the complexity of automotive systems increases, so do the risks associated with malfunctions, requiring a critical need for robust safety measures. Functional Safety (FuSa), as defined by ISO 26262, provides a framework for addressing these concerns at different stages of the safety lifecycle. The primary aim of FuSa is to develop Safety Mechanisms (SM) to detect faults and recover from them. The efficiency of these SMs is indicated by Diagnostic Coverage (DC), which represents the percentage of detected faults. In this context, there are several challenges in verifying the functional safety of automotive chips, especially with RTL designs. For example, identification of safe faults is one of the initial steps in FuSa verification. Discrepancies are observed in their classification when utilising different techniques such as Automatic Test Pattern Generation (ATPG), formal methods and fault injection simulation. This raises questions about the accuracy of overall results obtained from these tools as well. Varying outcomes from fault simulation EDA tools in classifying faults may result in different Automotive Safety Integrity Levels (ASIL) assigned to the component being assessed. This discrepancy would misrepresent the component's ability to reduce associated risks, highlighting the importance of conducting a detailed analysis and comparison of the tools.

The thesis provides a comprehensive evaluation of EDA tools utilized for Functional Safety Verification, focusing on RTL designs. Scripts are developed to automate fault simulation flows of two prominent FuSa EDA tools, XFS by Cadence and VC Z01X by Synopsys, and derive automatic comparisons. By comparing these tools, their strengths and limitations are analyzed. XFS exhibits limitations in fault propagation on input and output ports, resulting in the omission of certain fault scenarios. VC Z01X showcases faster fault simulation capabilities along with an extensive feature set for fault simulation, but lacks support for transient fault injection on a section of the fault subspace. By applying the automated tool flows on a FIFO design enabled with ECC, the DC obtained from XFS and VC Z01X are 68.96% and 80.47% respectively, showcasing a major difference. These findings highlight the importance of a holistic verification methodology that accurately estimates diagnostic coverage.

A novel verification methodology is proposed, which combines the strengths of XFS and VC Z01X to optimize the efficiency and accuracy of fault simulation. Leveraging VC Z01X's concurrent engine for parallel fault injection and XFS's capabilities to cover the unexplored fault space, this integrated approach provides comprehensive fault coverage. The flow also provides users the capability to update fault classification results based on manual analysis or designer inputs, thereby changing the DC as well. The verification methodology is applied to the AutoSoC benchmark suite, an automotive System-on-Chip with configurable SMs. Based on the results, additional SMs are implemented in the AutoSoC design - duplication of pipeline stages with temporal redundancy and ECC on internal memories. This leads to an estimated area increase of 1.4x as compared to the baseline design, but also results in the qualification of an ASIL C level component with a DC of 97.79%. The baseline verification flow included in the benchmark suite provides a DC of 98.36%, which is an over estimation of the actual coverage. The proposed methodology provides a more accurate coverage by taking into account the maximum possible fault space and considering transient faults as well. While there remains room for further improvement in verification methodologies, this framework effectively addresses the fault space required for FuSa verification and provides an accurate estimation of Diagnostic Coverage.

Nowadays, to reduce the dependence of devices on cloud servers, machine learning workloads are required to process data on the edge. Furthermore, to improve adaptability to uncontrolled environments, there is a growing need for on-chip learning. Limitations in power and area for edge devices have increased interest in low-cost neural network learning algorithms. However, as edge platforms are increasingly multi-core, new techniques are required to deploy learning algorithms on multi-core designs.
In this report, the performance of a low-cost multi-core on-chip learning platform with the local error learning (LEL) algorithm is evaluated. First, we reviewed state-of-art learning algorithms designed to solve the challenges of efficient neural network learning. We analyze these algorithms from the point of view of performance, hardware overhead, scalability, and the possibility of multi-core implementation. We propose a spatio-temporal learning framework for the combined use of LEL and e-prop. As a first proof of concept, we aim first at demonstrating multi-core LEL learning for image classification. Next, we constructed a software model suitable for multi-core on-chip driven by hardware requirements. With the software model, we then implemented the corresponding hardware and deployed it on a system-on-chip field programmable gate array (SoC FPGA) board to evaluate the performance. Results based on the CIFAR-10 image classification dataset show that the hardware design can fully reproduce the software runtime results. With a classification accuracy of 59.57\% after batch-size-1 on-chip learning, our design forms a stepping stone for the development of low-cost multi-core hardware that can adapt online to its environment.

Event-based cameras promise new opportunities for smart vision systems deployed at the edge. Contrary to their conventional frame-based counterparts, event-based cameras generate temporal light intensity changes as events on a per-pixel basis, enabling ultra-low latency with microsecond-scale temporal resolution, low power consumption at milliwatts level, and sparse information encoding where only dynamic objects trigger events, effectively excluding static background data. However, mainstream computer vision algorithms based on convolutional neural networks (CNNs) hardly exploit these advantages of event-based cameras. Recently, event graph neural networks (event-GNNs) have been proposed as the backbone for novel event-based vision algorithms. By treating events as graph data, GNNs are able to process events while preserving their spatiotemporal information and sparse characteristics. Further studies also revealed an event-driven computation workflow that translates an event stream into a dynamic, evolving graph, outlining a path toward low-latency event-based vision. Despite these promises, event-GNNs are still calling for dedicated hardware accelerators toward integrated solutions with real-time prediction latency and low power consumption for real-world edge intelligence.

In this thesis, for the first time, we proposed an event-driven GNN accelerator for low-power, high-speed edge vision. Through hardware-algorithm co-design, an event-driven GNN model is adopted for deployment on an edge FPGA platform without prediction accuracy loss. We also pointed out two novel optimizations, edge-free storage and layer-parallel computation, to further decrease memory footprints and processing latency. The proposed accelerator is implemented on the Xilinx KV260 System-On-Module (SOM) platform containing an UltraScale+ MPSoC FPGA, and benchmarked on-board. Targeting a car recognition task based on the NCars dataset, our accelerator achieves a prediction accuracy of 87.8%. Meanwhile, operating with a 6.86W board-level system power, the accelerator reaches an average 16μs prediction latency per event and runs 9.2× faster than its software counterpart running on an NVIDIA RTX A6000 GPU platform. Therefore, our event-driven GNN accelerator efficiently allows for both real-time and microsecond-resolution event-based vision at the edge.

Cardiovascular diseases (CVDs) are the top cause of death worldwide, and their diagnosis can be quickly and painlessly achieved through Electrocardiogram (ECG). The diagnosis of electrocardiogram has gradually evolved from manual diagnosis by doctors to one that can be realized using Artificial Intelligence (AI). Early AI still required manual extraction of features for ECG classification, but later Deep Neural Network (DNN) could automatically extract features during the learning process. With this technology, people can monitor heart movements in real-time through wearable devices. If there are any abnormalities, they can seek medical treatment in time to prevent death from sudden severe heart disease. However, for the wearable device, the energy consumption per classification by the traditional AI is so high that a limited battery cannot work for a long time.

To address this issue, this thesis adopts Spiking Neural Network (SNN) to do classification and implement the inference on the hardware. Compared with traditional Artificial Neural Network (ANN), SNN is highly energy efficient. According to the needs of SNN and its event-driven characteristics, the multi-threshold-based encoding scheme is proposed, which encodes the heartbeat into 54 spikes on average with less information loss. The SNN model is trained by ANN-SNN conversion with an accuracy of 97.42\%. After RTL coding, synthesis, and back-end implementation, the chip with encoding and inference functions achieves an energy consumption of only 57.88 nJ per heartbeat classification.

Spiking neural networks (SNNs), which are regarded as the third generation of neural networks, have attracted significant attention due to their promising applications in various scenarios. Based on SNNs, neuromorphic coprocessors, designed to emulate the structure and functionality of biological brains, hold the potential to revolutionize computing. However, these coprocessors encounter challenges related to adaptability and flexibility in various application environments once they are manufactured. To tackle this challenge, our project introduces a neuromorphic System-on-Chip (SoC), which seamlessly integrates a RISC-V CPU with an SNN coprocessor, utilizing sparse time-to-first-spike encoding (TTFS). The primary goal of this SoC is to facilitate the complete reconfigurability of the SNN coprocessor with the RISC-V CPU. By leveraging this neuromorphic SoC and successfully simulating the novel loop learning work model to achieve an accuracy of 92.2\% on the MNIST dataset, we demonstrate its capability to adapt the SNN coprocessor for various application scenarios, such as text recognition and face detection.

With the great application potential of the Internet of Things (IoT), a reliable power supply solution for IoT plays an important role during the development of IoT and other advanced applications. Among all the options including the electricity grid, batteries, and energy harvesting systems, the energy harvesting systems are considered with priority for the following advantages such as longevity and maintenance-free, environmental sustainability, integration with other electronics, continuous Operation, etc. Among all the energy harvesting systems with different energy sources from the ambient environment, thermoelectric energy harvesting systems have attracted much attention from researchers due to the qualities of ubiquitous temperature difference and stable power supply. Another reason for choosing thermoelectric energy is that with a bipolar temperature difference across the material, an input voltage of either positive or negative polarity is generated to be harvested during the day and night. This is to say, with a bipolar input thermoelectric energy harvesting system, the IoT devices can be powered for a super long period of 90\% of the whole day. However, the system has to solve the problem of low input voltage from the thermoelectric generator(TEG).

To design a real thermoelectric energy harvesting system, there are several indispensable blocks including the start-up block, maximum power point tracking(MPPT), zero current switching(ZCS), and polarity detection. The start-up block is necessary to be implemented to provide a higher voltage available to turn on the transistors and help the system get rid of the cold state. The MPPT block is exploited to track the maximum power point where the equivalent resistance of the DC-DC converter is equal to the internal resistance of the TEG. The ZCS block is implemented is make sure after the discharging of the inductor inside the DC-DC converter, the power switch is precisely turned off to minimize the synchronization loss. The polarity detection block makes sure that the system always works in a proper state to harvest either positive or negative input voltage.

This article presents a 2-switch bipolar boost converter with 40 mV Photovoltaic(PV)-assisted startup voltage for a thermoelectric energy harvesting system. The power stage is configured as a bipolar boost converter for the bipolar input with the implementation of complementary transistors. And a buck-boost converter is configured for the input polarity transition. The proposed system was fabricated in a 180-nm BCD process. The measurement results show that the system can start up from the cold state with a TEG voltage as low as 40 mV. It boosts input voltages ranging from 40 mV to 0.3 V and from -40 mV to -0.3 V to a 1.2 V output voltage across the load. It achieves a peak end-to-end efficiency of 93.0\% with a 0.26V input voltage or 89.0\% with a -0.27V input voltage. Moreover, end-to-end efficiencies are higher than 80\% for input voltages from 120 mV to 0.3 V and from -120 mV to -0.3 V.

With the introduction of event-based cameras, such as the dynamic vision sensor (DVS), new opportunities have arisen for low-latency real-time visual data processing. Unlike traditional frame-based cameras that capture entire frames at fixed intervals, each pixel in an event-based camera operates asynchronously, generating an event whenever its brightness change exceeds a certain threshold. Although DVS sensors inherently surpass traditional frame-based cameras in capturing transient, high-speed phenomena, their performance bottleneck is usually located in their address event representation (AER) readout interfaces. The commonly used row-scanning synchronous AER, which encodes events in a full row at once, offers high throughput. However, this approach also introduces inherent delays that limit its use in applications requiring high temporal resolution. Conversely, while AER schemes based on asynchronous digital circuits surpass synchronous schemes in temporal resolution, their event-by-event transmission approach limits their overall throughput.

This work proposes a novel high-speed asynchronous AER interface, leveraging spatiotemporal correlations in DVS event-based data, to optimize the tradeoff between temporal resolution and throughput. Supported by the recently proposed open-source asynchronous design toolkit (ACT) flow for asynchronous digital circuits, we propose an address fuser to be integrated into the hierarchical token ring (HTR) AER scheme. This address fuser creates a spatiotemporal window to exploit the inherent spatiotemporal correlations in DVS data. After verification at both switch- and transistor-level simulations, we benchmarked our design against the conventional HTR AER scheme using a representative set of input scenarios. Our design achieved 196% of the throughput for multi-event transmissions when all pixels were activated simultaneously, at the expense of an acceptable 18% latency increase for single-event transmissions with a 10-ns temporal window.

This thesis focuses on identifying and classifying defects in STT-MRAM technology using novel and machine learning approaches. The thesis discusses the basic principles of STT-MRAM and the semiconductor chip manufacturing process and test stages. The research aims to develop novel methods and explore machine-learning approaches to diagnose defects in STT-MRAM devices. The current defect identification methodologies have shown certain cost, speed, and scalability limitations. The thesis presents DAT-based and ML-based Diagnosis methodologies to identify and classify STT-MRAM unique defects to address these challenges. The methods are evaluated and validated on experimental wafers performed at IMEC in Leuven, Belgium.

DAT-based Diagnosis involves automated defect identification in STT-MRAM based on identifying features automatically extracted from specialized measurements targeting the unique defects, Pinhole, Intermediate State, SAF Flip, and Back-Hopping. ML-based Diagnosis uses machine learning techniques to classify defects using MTJ features extracted from low-cost measurements. Data collected from electrical measurements on experimental STT-MRAM devices serve as the basis for evaluating the developed methodologies. The thesis also discusses data analysis, including data visualization, feature correlations, and outlier analysis for future research. Furthermore, a machine learning training process is performed, including hyperparameter optimization and evaluation using F-score and B-accuracy metrics to assess the model's performance and the ability to generalize on unseen data.

DAT-based Diagnosis aims to maximize the defect detection accuracy at the expense of measurement costs. In contrast, ML-based Diagnosis minimizes the measurement cost while maximizing the detection accuracy for robust and balanced classification. However, the DAT-based Diagnosis is not verified using PFA to validate the defect types identified by the developed methodology. Furthermore, the ML-based Diagnosis uses training data labeled by the unverified DAT-based Diagnosis approach to train machine learning models. Despite these limitations, the results have shown valuable insights into defect identification and classification, proving a robust framework for diagnosing STT-MRAM devices. Additionally, a scientific paper is submitted on march-based diagnosis, adapting the DAT-based Diagnosis method to industrial chips that are limited in extracting the identifying features.

This thesis delves into reconfigurable computing architecture (RCA) design based on emerging embedded non-volatile memory (eNVM) technologies. Traditional Field-Programmable Gate Arrays, while efficient, face inherent limitations when it comes to power consumption and reconfigurability, primarily due to their set amount of resources and reliance on SRAM cells. Emerging eNVM technologies, such as STT-MTJ, ReRAM, and FeFET, offer potential alternatives, each with unique benefits and drawbacks. In this research, we introduce a novel RCA architecture built upon FeFET eNVM technology, which we called the 'Unified Tile'. This architecture is distinctive for its 2D layout of homogeneous tiles, these tiles integrate the three primary functions of an RCA: memory, interconnect, and logic. Our proposed design emphasizes the potential advantages of eNVM technologies over conventional SRAM-based FPGA components.

To validate our design, we employ an event-based simulator developed on the SystemC framework. Through evaluations and benchmarks, our 'Unified Tile' demonstrated notable improvements in power, area, and delay metrics compared to traditional FPGAs. Moreover, when compared with other state-of-the-art eNVM-based RCAs, our architecture showcased competitive, performance. These findings underscore the potential of eNVM-based RCAs as a viable alternative to SRAM-based FPGAs. This research shows the potential of eNVM technologies in reconfigurable computing architectures, with an emphasis on a FeFET-based design. It has also highlighted areas of concern, especially in programming latency, for these emerging technologies.

Resistive random access memory (RRAM) is an emerging memory technology that has the potential to replace dynamic random access memory (DRAM) or FLASH. The current memory technology suffer from scalability issues. RRAM can be used as potential replacement for Flash and DRAM. RRAM stores information using resistance states instead of charge. RRAM is non-volatile memory, power efficient, scalable and compatible with the current CMOS process.
Before RRAM can be commercialized the quality of RRAM devices needs to be guaranteed. For this we need to diagnose RRAM devices. The diagnosis allows us to improve the manufacturing process as well as built defect models for memory testing. The traditional fault models do not incorporate the non-linear behaviour of the RRAM device. As a result, tests are created for the wrong test space resulting in a lower yield and more test escapes. To increase the yield and create more reliable fault models, defect models that incorporate the physical defect of the RRAM device are required. To ensure the manufacturing quality of the RRAM devices and for memory testing of RRAM the characterization and diagnosis of RRAM is required. The electrical characterization of RRAM is cheap, fast and is used to evaluate the performance of RRAM. For diagnosis electrical characterization has not been used before.
This work uses the electrical characterization of RRAM to automatically identify defective RRAM devices which can be used for diagnosis. For the defect identification, the key parameters are determined. To assess the performance of the defect identification algorithms the RRAM devices are labelled manually. In total five methods have been implemented to automatically label defective RRAM devices. A statistical analysis is performed on the RRAM devices. Using the labelled data the devices are compared to a nominal device to identify defects in RRAM. Furthermore, K-means, KNN and a CNN algorithm is applied to RRAM. The classification algorithms allow the automatic identification of defective RRAM devices which can be used for diagnosis.
The metrics used for the statistical analysis are insufficient to accurately identify defective RRAM devices. The nominal device method classifies 81% of the device correctly using the euclidean algorithm. The best performance is obtained for the supervised learning algorithm. K-NN classifies 94% of the cycles correct and 84% of the devices. If the data is not labelled the unsupervised learning algorithm can be used. Kmeans classifies 79.6% of the devices correctly which is slightly worse than K-NN. The CNN classifies 67% of the devices correctly using 20 epochs. However, the CNN has not yet been optimized and needs to be improved. For unlabelled data, the unsupervised learning algorithm should be used and for labelled data the K-NN. The electrical characterization of RRAM devices using machine learning looks promising and is much cheaper compared to optical characterization and memory tests. If in the future the defective devices can be linked to the underlying defect, this will lead to cheaper diagnosis of RRAM devices and allow the creation of accurate fault models.

Depth sensing technology has developed rapidly recently due to its broad applications. Time-of-Flight (ToF) is a popular technology in depth sensing because of its advantages in high measuring accuracy and low complexity in image processing. ToF technologies are divided into two kinds: indirect time-of-flight (iToF) and direct Time-of-Flight (dToF). Compared to the iToF, dToF can detect targets at a longer distance by directly calculating the flight time of the laser. To obtain time information, the dToF system requires a Time-to-Digital Converter (TDC). This thesis proposes a system-level model to optimize the TDC parameters for a dToF system used in an autofocus system of a mobile phone. According to the simulation result of the system modeling, a ring-based TDC is chosen and built using a shared and duty-cycled Voltage-Controlled Oscillator (VCO). To decrease the DNL of the TDC, chopping comparators are used in this design. In addition, to save power and area, a new method called double sampling is used to align the coarse and fine phases of the ring based TDC. The proposed TDC achieves a resolution of 100 ps and a DNL of −0.27/+0.37 and an average power of 0.179 mW/TDC, which are smaller than that of state-of-the-art TDCs used in dToF systems. SMIC 55BSC technology is used to design and tape out the TDC.

This thesis focuses on the design of a high input impedance sensor readout system based on a continuous-time sigma-delta modulator with finite-impulse-response digital-to-analog converter feedback.

Both the system-level and circuit-level design techniques of this system are investigated. The concept and design methods of finite-impulse-response digital-to-analog converters are introduced. The first integrator with source degeneration resistors and an input Gm-boosting cell is designed to achieve high input impedance and linearity. Both simulation and post-layout simulation results confirm the expected effective number of bits of 15 bits in the readout performance. The design is fabricated in a standard 180nm CMOS technology.