The rapid development of power electronics has challenged the thermal integrity of semiconductor packaging. Further developments in this domain can be supported significantly by utilizing fast and flexible thermal characteristic evaluation. This study employs the transient dual interface method (TDIM) to characterize and compare the thermal resistance of Ag- and Cu-sintered die-attach joints using an in-house developed thermal test chip (TTC). The proposed TTC with 82.5% active area achieves a temperature sensitivity of 12 Ω/K and maximum power of 360 W per cell, which are 50% and 44% higher than the state-of-the-art, respectively. The uniformity of the temperature distribution (1 °C at 68 W) is verified by infrared thermography. The cost-effective manufacturing process allows the design to be applied to any substrate, such as SiC or GaN. Ag and Cu sintering is performed to bond the TTC on a Cu substrate, and the junction-to-case thermal resistance of the sintered structures is extracted. The lowest junction-to-case thermal resistance of 0.144 K/W is measured for the device sintered using Ag paste. Meanwhile, the Cu sintered structure exhibits a comparable value of 0.158 K/W. The proposed TTC in combination with TDIM accelerates the introduction of novel and cost-effective materials such as Cu.@en

Wide bandgap (WBG) semiconductor technologies enable significant progress in the emergence of power modules. Power cycling at elevated temperatures causes crack or delamination failure, especially at the die-attached bonded interface in the long term. Therefore, the in-situ reliability investigation of power modules, materials, and semiconductor packages is of great significance for modern industries. The silicon carbide's higher bandgap energy, intrinsic thermal conductivity, and mechanical strength make it a great candidate for the next generation of semiconductor, designed to operate in harsh conditions. In this study, a thin-film reconfigurable silicon carbide (SiC) thermal test chip (TTC) is designed and fabricated for reliability assessment in harsh environments. The proposed TTC realizes in-situ power/thermal cycling tests at elevated temperatures as well as characterization of novel materials such as nanoparticle-based sintering materials in die-attach technology and high-temperature-compatible epoxy molding compounds. The chip is equipped with thin-film platinum microheaters to realize modular power mappings, and platinum resistive temperature detectors (RTD) to examine the thermal reliability by monitoring the precise changes of the internal junction-to-case thermal resistance.

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This paper reports the design and fabrication of a 4H-SiC CMOS readout circuit enabling monolithic integration of silicon carbide (SiC) sensors and circuits. Compared to conventional Si electronics, 4H-SiC integrated circuits can sustain operation in harsh conditions such as higher temperatures and radiation levels. The proposed amplifier performance is well balanced through the temperature range of 25 °C to 400 °C. Compared to state-of-the-art, the proposed SiC readout circuit does not include any off-chip components. The amplifier is fully differential, and hence shows improved common-mode rejection and signal-to-noise ratio (SNR). It can be monolithically integrated with SiC sensors in a scalable SiC technology.@en

This study presents the design and fabrication of an in-package relative humidity sensor for epoxy molding compound (EMC) packages. The sensor comprises shielded interdigital electrodes (SIDE) for in-situ monitoring of humidity absorption/desorption in the package encapsulation layer. A novel approach is employed in the device fabrication to maximize the electrical field lines to pass through the EMC and enhance the sensitivity. The manufactured wafer includes 6×6mm2 dies, each containing six identical capacitive sensors with an area of 480 × 620 μ m2. SU-8 through polymer vias (TPVs) with high aspect ratio were created to locally mold the sensors by EMC. The linear capacitance change with the relative humidity level is simulated in COMSOL Multiphysics. Three designs were compared, and the calibration results show the capacitance value of 1.54 pF and 5.85 pF before and after molding, respectively. The capacitance value stays within the range of 5.85 to 5.86 pF with less than 7 aF variation under different biasing voltages, indicating the stability and robustness of the capacitance.

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This study presents a novel manufacturing process and design towards an enhanced sensitivity of an in-package relative humidity sensor. The device comprises multi-width interdigital electrodes which make oxide pillars appear during wet chemical etching in the fabrication process. Those oxide pillars appear only in wider areas while completely etched away in narrower areas providing semi-floating metal fingers. Therefore, after wafer molding, the packaging encapsulation material such as the epoxy molding compound covers larger area around the electrodes and increases the sensitivity by confining more of the electrical field lines. The results confirm the enhanced sensitivity of the proposed humidity sensor for characterization and monitoring of the aging properties of packaging encapsulation materials.@en

With an increasing demand for high-power electronics, the need to meet stringent automotive norms and better understand the critical failure mechanisms are crucial in order to improve their reliablity. To that end, we developed an in-situ reliability monitoring setup capable of actively measuring the thermal performance of the package during lifetime testing. A Thermal Test Chip (TTC) assembled into a Power Quad Flat No-lead (PQFN) package was employed as a test vehicle for non-destructive reliability assessment. The TTC comprises resistive heaters as a heat source and resistive temperature elements for measuring the thermal response. The transient thermal behavior was evaluated based on the contribution of heat source to a temperature field, and the temperature distribution was measured at multiple spatial positions. The experimental results provide insights into the thermal properties’ influence on the thermal behavior of the package. A compact electro-thermal model based on analogies was developed to deconvolute and analyze the transient thermal measurements. The results of the compact model correlate with the experimental measurements, and the model’s accuracy was verified using finite element simulations. The development of such thermal characterization experiments and computationally inexpensive models assist in further understanding the impact of failures in advancing high-power density electronics.@en

This paper focuses on the design and fabrication of a new programmable thermal test chip as a flexible and cost-effective solution for simplification of characterization/prototyping of new packages. The cell-based design format makes the chip fit into any modular array configuration. One unit cell is as small as 4x4 mm2, including 6 individually programmable micro-heaters and 3 resistance temperature detectors (RTDs). All micro-heaters and sensors have 4-point Kelvin connections for improved measurement accuracy. The chip contains 2 metal layers: 100 nm thin-film Titanium to create micro-heaters and RTDs, and 2 μm Aluminum to add single bump measurement units and daisy chain connections. These structures facilitate bump reliability investigations during thermal/power cycling tests in flip-chip assembly technology. The calibration curves of RTDs show a sensitivity of 12 $\Omega$/K which is improved by 50 percent compared to the state-of-the-art TTC. The proposed design provides higher spatial resolution in thermal mapping by accommodating 3 RTDs per cell. The dense configuration of micro-heaters increases the uniformity of the power dissipation, which enhances the accuracy of thermal interface material (TIM) characterizations. The steady-state infrared (IR) thermography of a 20x20 mm2 TTC, including 150 active micro-heaters, verifies the promising uniformity of the heat profile over the chip surface.@en