As 5G is rapidly growing, wireless communication systems require wideband, compact and highly efficient power amplifier modules (PA) to drive the base station antenna arrays. Doherty PAs are implemented in most base stations. The final stage in these power amplifier modules has high supply voltages (28-50 V) to generate a high output power of >20 W at reasonable output impedance levels. This work replaces the ‘classical’ single-ended cascode PA to drive the Doherty PA, with a series push-pull (or totem-pole) PA to increase the efficiency and bandwidth of the driver. The series push pull designs can reach peak efficiencies of 70.7%, which is about 10 percentage points higher than the efficiency of the single-ended PA. To ensure that a fair comparison is made between the designs, the series push-pull designs operate at 5 V and 10 V supply, in order to generate an output voltage swing of 5 V and 10 V respectively. This is compared to the single-ended PA with a 5 V supply and 10 V output swing. Simulation results show that the series push-pull design does indeed increase the efficiency of the driver whilst having minimal AM-AM distortion (<1 dB) at the design frequency of 3.6 GHz.

This work describes a fully digital transmitter (DTX) for 5G mMIMO base stations that combines the strengths of high-speed digital CMOS with the high-power capabilities of a Monolithic Microwave Integrated Circuit (MMIC) high-voltage technology. This technology platform offers high integration and scalability for implementing Radio Frequency Digital-to-Analog Converters (RF-DACs). To facilitate the digital operation of the gate-segmented output power stage, a custom VT-shifted LDMOS technology has been utilized. The relatively high output capacitance of the LDMOS devices makes digital class-C operation the preferred class of operation to achieve high efficiency with good linearity metrics for the digital power amplifier (DPA). In this work, we analyze this operation, assuming a trapezoidal-shaped current profile, which allows investigation of the impact of the non-zero rise and fall times on the theoretical (normalized) output power and drain efficiency.
To drive the gate segments in this custom VT LDMOS technology with a gate-to-source voltage (VGS) swing of 2.2 V, a driver is proposed comprising: inverter chains, a level shifter, and a high-voltage output buffer. This driver is fully digital and can be implemented using thin-oxide bulk CMOS devices whose VDD is limited to 1.1 V. A model of the DTX comprising only the drivers and DPA at the circuit level is created in ADS to evaluate the output power, drain efficiency, and system efficiency. The DTX is simulated at 3.5 GHz full power and achieves an output power of 19.79 W/23.43 W, a drain efficiency of 67.28%/59.22%, and a system efficiency of 60.34%/54.48% with a non-empirical and empirical model of LDMOS, respectively. Rise and fall times of around 20% of the RF cycle (tr = tf = 0.2/fc) are found to be the most suitable in terms of power consumption and system efficiency.

Wireless data traffic is projected to steadily increase in the near future, necessitating the demand for transceivers with higher linearity and efficiency. Digital power amplifiers have the potential to achieve these higher efficiency demands while digital pre-distortion can be used to improve their linearity. Digital pre-distortion requires a highly-linear wideband observation receiver to down-convert and monitor the output of the transmitter. An observation receiver architecture that relies on baseband error-detection has been previously proposed by ELCA to reduce the stringent requirements on the analog-to-digital converter (ADC) in such an observation receiver. This thesis work presents a novel extremely-linear wideband voltage-domain harmonic-reject mixer targeting these observation receiver applications. The choice for a voltage-domain mixer instead of a current-domain mixer is first discussed. Three novel voltage-domain mixer topologies are then evaluated for their advantages and disadvantages, yielding the preferred topology for implementation. This circuit was designed in TSMC40nm thin-oxide CMOS technology yielding promising performance metrics when compared to similar state-of-the-art publications in the open literature; specifically in domain of observation receiver applications.

N-path filters promise to miniaturize RF receivers by replacing various fixed off-chip filters with a single programmable on-chip filter. This research investigates some of the issues of receivers with N-path filters under strong blocker conditions: reciprocal mixing and inherent nonlinearity. First, a technique for reciprocal mixing cancellation is explored and shown to be impossible using only mixers and baseband impedances. Second, the inherent nonlinearity of both bandpass and notch N-path filters are simulated and modelled. To validate this approach, a highly linear receiver is proposed and designed in 40nm CMOS. The receiver has a bandpass common gate architecture, with a notch filter in the feedback path, improving linearity. The filter is isolated using buffers, improving LO leakage. The common gate stage is IM3 compensated to obtain good
linearity (OOB IIP3 >20 dBm).

This work presents a highly linear quadrature down-converter topology intended for the linearization of digital Transmitters(DTX). By integrating it with a DTX, a fully integrated on-chip output-signal correction loop comes closer to its realization. The proposed down conversion architecture can measure the errors introduced by the non-linearity of the transmitter, rather than the transmitter output itself. These errors are determined by comparing the downconverted transmitter output signals with its analog ideal baseband I and Q reference signals. The reference signals are provided by low-power digital-to-analog converters(DACs), using the same IQ data input as the power DTX. This approach reduces the resolution/dynamic range requirements on the trans-impedance-amplifier (TIA) and analog-to-digital converters(ADCs) since the error signals have a reduced dynamic range compared to the transmitter’s output signal itself. These lower requirements on the ADCs and elimination of off-chip couplers and filter sease the integration of a complete digital pre-distortion (DPD) correction loop in future DTX implementations. As the core of this thesis work, a linear harmonic rejection mixer was designed. It uses resistors inits mixer branches to implement the proper currenct scaling needed for harmonic rejection (HR). The resulting HR mixer avoids the unwanted down-conversion of the higher harmonics of the DTX to the base band frequencies of interest. Also, atrans-impedance amplifier was designed with the proposed passive mixer. These TIAs are based on an inverter topology for maximum tranconductance and were biased for optimal linearity and offered a bandwidth over 1.8GHz. The proposed DTX error-detection architectureis implemented in the current domain. Performing the subtraction before the TIA drastically reduces the voltage swing at the input of the TIA, benefiting the linearity of the mixer and reference DAC. The overall HR-mixer configuration is simulated for its linearity, yielding an IIP3 of 49dBm, which to the best of the author’s knowledge, is the best-reported linearity for high bandwidth down-converting applications.

Many applications require wide bandwidth transmitters, but unfortunately, they usually have way less than 50% average drain efficiency for their modulated signals. This low efficiency is a significant drawback in all wireless applications, both for battery power devices and base stations. The Doherty radio frequency (RF) power amplifier architecture is widely used to enhance the average efficiency for modulated signals in base stations. Its popularity is due to its relatively cheap and simple hardware and its suitability to handle high-power wideband modulated signals. However, even Doherty amplifiers often have less than 50% average efficiency and are restricted in their RF bandwidth.
This thesis reviews recent research on the Doherty power amplifier (DPA) topology and discusses possible power and bandwidth efficiency improvements. In the second part of the thesis, another topology is introduced, which also provides Doherty-like behavior. That topology is called a Pseudo Doherty Load Modulated Balanced Amplifier (PD-LMBA). The performance of PD-LMBA is compared with “conventional” DPAs. Circuit design examples of DPA and PD-LMBA are given. The thesis concludes with a PD-LMBA prototype design, which appears to be very promising in its wideband performance.

This thesis investigates the performance limits and design challenges of two current-mode front-end concepts that target WiFi and mm-wave 5G applications, respectively. The first concept is a power amplifier (PA), which operates at 2.4GHz and is driven by a direct-digital RF modulator (DDRM). A design for the PA, which also includes a parallel-combining transformer (PCT), was proposed, taped and tested in the QUBiC Gen8 technology of NXP Semiconductors. The measured results yield a peak output power of 27dBm, power efficiency of 20%, and an adjacent channel power ratio (ACPR) of -33.05dBc. In the other concept, the DDRM drives a power mixer (PMIX) which up-converts the DDRM signal to mm-wave frequencies. For the PMIX-based front-end, multiple linearity enhancement techniques were proposed and evaluated using simulations. For both current-mode front-end concepts, an extensive analysis on the theoretical output power and power efficiency limit was performed. Although current-mode operation has a high linearity potential, fully reaching this potential turns out not to be trivial, due to various device non-idealities and imperfect impedance matching.

CMOS technology is one of the feasible solutions to meet the world’s growing demand for high data rates because it offers the prospect of SoC at a low cost. But, the PA forms the major bottleneck in making SoC because the PAs in high data rate wireless communication systems have the requirement of high-efficiency and good linearity even at backed-off power levels. Currently, PAs are mostly of classes A and B. Both of these are linear, but peak efficiencies are only 50% and 78% respectively. This thesis focuses on implementing Continuous Class F (CCF) PA for WiFi 802.11n over the bandwidth 2.1 - 2.7 GHz, which meets the requirement of high efficiency and good linearity even at backed-off power levels. The CCF PA overcomes Class F’s disadvantage of limited bandwidth as well as maintains peak efficiency of 90.7% over the entire bandwidth. The designed PA has four main blocks: the driver, inter-stage matching, output network, and output stage. The procedure to implement each of these blocks is explained extensively in chapters 3, 4, 5, and 6. The layout of the chip is carried out in TSMC 40 nm, and the chip size is 1.4 mm2. From simulations, the CCF PA has a maximum efficiency of 30 % and EVM of -25 dB at 3 dB back-off across the bandwidth 2.1 -2.7 GHz. The tapeout of the chip is planned in March 2021. Later, the chip can be tested and simulation results will be validated. To the best knowledge of the author, this is the first CCF chip at 2.4 GHz band.

This thesis presents the development of circuits and systems for fast wireline transceiver links that will enable a move towards highly integrable RF digital-to-analog converters. A new perspective on the analysis of bit error rates in wireline links leads to the PAM spectral design space chart: a novel, visual system design analysis tool for PAM wireline circuit designers. Moreover, a <2 mW/Gbps/lane, 10 Gbps wireline transmitter has been designed and taped-out in 40 nm CMOS. The proposed inherently pipelined 16:1 multiplexer and current mode logic driver design procedure are the key enablers for this performance. Finally, for development of a 10 Gbps wireline receiver, a novel self-synchronized receiver design is proposed that removes the need of a classical clock and data recovery loop. At its core, this receiver comprises the design of a high-speed two-tail comparator and an asynchronous metastability detection loop.

The ever increasing demand for faster data rates combined with the need for higher levels of integration, while keeping the production and operation cost to a minimum leads to the requirement of an efficient high bandwidth digital transmitter architecture. With the shortcomings of both polar and cartesian architectures, a new architecture is introduced.

In 5G transmitters, high efficiency, high linearity, and compatibility with MIMO and beamforming techniques are of utmost importance. Typically, enhancement techniques like supply modulation or load modulation are used when dealing with envelope modulated communication signals, which increasingly have high peak-to-average-power ratios (PAPR). Supply modulation is most favored in handsets. Techniques like "Envelope Tracking (ET)" or "Envelope Elimination and Restoration (EER)" are employed to generate high efficiency over a large power back-off range. These techniques are robust to antenna impedance variations compared to load modulation techniques like Doherty. However, the downside of supply voltage modulation is the need for a dynamic supply modulator. Such supply modulators are very difficult to implement for systems with video bandwidths >20MHz. For modern communication systems like 5G, video bandwidths for both the base stations and handsets are drastically increasing (up to ~1GHz). 5G communication is also going to operate at very high frequencies, commonly known as mm-wave. This degrades the efficiency of the transmitter because of increased losses in the output conductance of the active device and from any power combining network. Furthermore, due to the use of (massive) MIMO/smart-antenna techniques in these 5G base stations, there will also be undesired time-fluctuating antenna impedances due to PA back-coupling through the antenna array, which are extremely difficult to handle in efficiency enhancement techniques based on load modulation. In this thesis, a new type of wideband "supply voltage modulation" has been investigated. The aimed concept uses multiple constant supply voltages rather than a single time variant dynamic voltage supply. Several "parallel" PA devices are connected to different DC supply voltages while their RF output terminals are AC connected. The PA connected to a lower DC supply is used in the low power region, while the PA with a higher DC supply is used in the high power region. This ensures that the DC power consumption is output power dependent. By gradually controlling the amplifier branches through their RF inputs, proper transitions can be made between the different amplifier branches (i.e., from low power to high power region and vice versa)

Recent years have seen an exponential growth in required wireless data capacity. This exponential growth is expected to continue, while it is unsustainable if the power consumption associated with it will grow at the same rate. This calls for better power efficiency, which can usually be found in polar power amplifier architectures. This thesis focuses on the feasibility of a power RF-DAC, with as main focus to seek improvement in power efficiency. As all information up to the RF output is in the digital domain the design will be frequency agile, meaning that operation frequency is only dependent on the external matching network.
As starting point an existing LDMOS technology is considered to implement a power Digital-to-RF-Amplitude Converter (DRAC) with a dedicated CMOS driver. As first demonstrator these two chips could be connected using flip-chip bonding. The proposed combination allows a maximum operation frequency of 3 GHz, providing a peak fundamental output power of 16,6 W with a drain efficiency of 64,4 % at the maximum operation frequency. Since the CMOS driver operates in Class-D a significantly lower average driver power consumption is expected compared to an analog system where a Class-A or Class-AB predriver would be used. This promising concept can change the way how future transmitters could be constructed. In conclusion a performance outlook will be given if a dedicated high power silicon technology that can feature the CMOS drivers would be available for 4G/5G applications.

In this thesis, a new RF Power Amplifier design is proposed that targets for improving the efficiency profile of classical RF Amplifiers. This RF Power Amplifier is especially designed for modulation schemes that need a PA with high PAPR. The PA consists of two different stages that will be digitally controlled. One of these stages has an optimized efficiency profile for supporting input signals with nominal power and the other stage has an optimized efficiency profile for supporting input signals with peak power. The PA has been designed with GaN HEMT's which perform very well at high frequencies while delivering high power.

The PA has been designed to perform optimally for frequencies around 100 MHz. Simulations show that at peak power, which is 40 dBm for this amplifier design, the PA has an efficiency of 63.5%. At 6 dB power back-off, the PA has an efficiency of 65.5%. The PA has a gain of approximately 20 dB at peak power level and approximately 18 dB at nominal power level. Furthermore the stability of the PA is optimized for the carrier frequency of the input signal. At 100 MHz the Rollet Stability Factor K is of magnitudes higher than unity which guarantees the stability of the circuit.

Furthermore a PCB has been developed to do some investigations in how this new PA design will perform in practice. Measurements on this PCB show that in power back-off a maximum efficiency of 63% can be reached. Results of the performance at peak power show that the efficiency reaches a maximum level of 37%. A possible reason for this is insufficient suppression of undesired harmonics.

This is an IR-UWB pulse generator design, which is based a switched-capacitor RF-DAC. This chip is taped out by Global Foundries 40nm CMOS LP process.

Automotive RADARs have gained popularity recently as a means to sense obstacles and avoid collisions, thus preventing loss of life related to vehicular incidence. Research in object detection is increasingly tending towards the 77GHz automotive RADAR band, owing to the availability of larger bandwidths, resulting in high range resolution. Another advantage of the frequency band comes from the absorption properties of the atmosphere, which limits the range and allows multiple vehicles to use RADARs with minimum interference.
A Power Amplifier is the most power hungry block in a transmitter-receiver chain
and must be designed for high power efficiency, in order to mitigate radiative and more importantly heat losses. However, achieving high efficiency within the target automotive RADAR band proves to be challenging, specifically in case of integrated CMOS PAs. This thesis presents a study of Injection Locked Power Amplifiers (ILPA) in detail and proposes an architecture to meet the RADAR specification. The thesis also highlights passive loss models and provides a theoretical analysis of multi-stage power amplifiers by deriving an expression for the total efficiency of such a PA.
Furthermore, this thesis proposes a design procedure and highlights the design process in 40nm CMOS technology. Emphasis is also placed on the study of the active device available in the PDK. The designed integrable PA shows a peak output power of 13dBm with a PAE=17% and gain=16dB within a 5GHz band centered around 78.5GHz.