The spin of a single electron or hole provides an attractive candidate for implementing a quantum bit when confined in a semiconductor quantum dot. Such a spin qubit is characterized by long coherence and short gate times. High-fidelity single and two-qubit operations have been demonstrated as well. Additionally, semiconductor quantum dots have a small footprint (~ 100 nm x 100 nm) and their fabrication employs techniques similar to processes commonly used in modern semiconductor technology foundries. This promises the realization of dense qubit arrays, leverage through industrial fabrication, and direct co-integration with classical control circuits.

Thus far, one-dimensional quantum dot arrays have been studied extensively. Yet, only by realizing two-dimensional quantum dot arrays the small footprint of quantum dots is fully exploited. Also, due to their small size quantum dots are extremely sensitive to their local environment and fabrication imperfections. In current devices, an individually tailored set of gate electrode voltages is required for each quantum dot to confine a single charge. The limited space available for routing these voltages on the device, coupled with the associated overhead in required voltage sources, presents a challenge in scaling quantum dot arrays, especially two-dimensional arrays.

This thesis focuses on two-dimensional quantum dot arrays and gate voltage uniformity. The first part (chapter 3 and 4) reports the realization of two-dimensional quantum dot arrays in a silicon/silicon-germanium (Si/SiGe) and a germanium/silicon-germanium (Ge/SiGe) heterostructure. Afterward (chapter 5 and 6), a novel all-electric method is presented to achieve increased homogeneity of the required gate voltages.

In chapter 3 a 2 x 2 quantum dot array in a Si/SiGe heterostructure is presented. It is tuned to be occupied by a single electron per quantum dot reaching the (1,1,1,1) charge state. Dedicated barrier gate electrodes on the device allow for controlling the interdot tunnel couplings between neighbouring quantum dots from about 30 ueV up to approximately 400 ueV as characterized through polarization line measurements.

In chapter 4 the focus is shifted towards a more scalable gate architecture for two-dimensional quantum dot arrays. It is inspired by random access architectures that are found in classical electronics. Specifically, a 4 x 4 quantum dot array in a Ge/SiGe heterostructure with shared gate electrode voltages is introduced. In this device, an odd charge occupancy is reached with either one or three holes in all 16 quantum dots simultaneously. Also, two shared barrier gate electrodes are placed between adjacent quantum dots. These enable selective control of the interdot tunnel coupling from less than 3 GHz to more than 10 GHz.

Spatial fluctuations in the electric background potential still limit the scalability of such a shared control array. Therefore, chapter 5 introduces a new method to increase the electrical uniformity in quantum dot devices. The presented method is based on applying stress voltages to the device gate electrodes. It enables the tuning of pinch-off voltages in quantum dot devices over hundreds of millivolts. Afterward, the new pinch-off voltages remain stable for hours at least. The method is used to homogenize the pinch-off voltages of the plunger gates in a linear array designed for four quantum dots. It reduces their spread by one order of magnitude from 153 mV to 20 mV.

Motivated by this demonstration, in the experiment presented in chapter 6 the stress voltage tuning method is applied to control the plunger gate voltages required to reach single electron occupation in a quantum dot array. In a double quantum dot, a stable (1,1) charge state is reached at identical and predetermined plunger gate voltage and for various interdot couplings. Finally, by applying stress voltages a 2 x 2 quantum dot array is tuned such that the (1,1,1,1) charge state is reached when all plunger gates are set to 1 V.@en

The electrical characterisation of classical and quantum devices is a critical step in the development cycle of heterogeneous material stacks for semiconductor spin qubits. In the case of silicon, properties such as disorder and energy separation of conduction band valleys are commonly investigated individually upon modifications in selected parameters of the material stack. However, this reductionist approach fails to consider the interdependence between different structural and electronic properties at the danger of optimising one metric at the expense of the others. Here, we achieve a significant improvement in both disorder and valley splitting by taking a co-design approach to the material stack. We demonstrate isotopically purified, strained quantum wells with high mobility of 3.14(8) × 10⁵ cm² V⁻¹ s⁻¹ and low percolation density of 6.9(1) × 10¹⁰ cm⁻². These low disorder quantum wells support quantum dots with low charge noise of 0.9(3) μeV Hz^−1/2 and large mean valley splitting energy of 0.24(7) meV, measured in qubit devices. By striking the delicate balance between disorder, charge noise, and valley splitting, these findings provide a benchmark for silicon as a host semiconductor for quantum dot qubits. We foresee the application of these heterostructures in larger, high-performance quantum processors.

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The small footprint of semiconductor qubits is favorable for scalable quantum computing. However, their size also makes them sensitive to their local environment and variations in the gate structure. Currently, each device requires tailored gate voltages to confine a single charge per quantum dot, clearly challenging scalability. Here, we tune these gate voltages and equalize them solely through the temporary application of stress voltages. In a double quantum dot, we reach a stable (1,1) charge state at identical and predetermined plunger gate voltage and for various interdot couplings. Applying our findings, we tune a 2 × 2 quadruple quantum dot such that the (1,1,1,1) charge state is reached when all plunger gates are set to 1 V. The ability to define required gate voltages may relax requirements on control electronics and operations for spin qubit devices, providing means to advance quantum hardware.

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The efficient control of a large number of qubits is one of the most challenging aspects for practical quantum computing. Current approaches in solid-state quantum technology are based on brute-force methods, where each and every qubit requires at least one unique control line—an approach that will become unsustainable when scaling to the required millions of qubits. Here, inspired by random-access architectures in classical electronics, we introduce the shared control of semiconductor quantum dots to efficiently operate a two-dimensional crossbar array in planar germanium. We tune the entire array, comprising 16 quantum dots, to the few-hole regime. We then confine an odd number of holes in each site to isolate an unpaired spin per dot. Moving forward, we demonstrate on a vertical and a horizontal double quantum dot a method for the selective control of the interdot coupling and achieve a tunnel coupling tunability over more than 10 GHz. The operation of a quantum electronic device with fewer control terminals than tunable experimental parameters represents a compelling step forward in the construction of scalable quantum technology.

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Highly uniform quantum systems are essential for the practical implementation of scalable quantum processors. While quantum dot spin qubits based on semiconductor technology are a promising platform for large-scale quantum computing, their small size makes them particularly sensitive to their local environment. Here, we present a method to electrically obtain a high degree of uniformity in the intrinsic potential landscape using hysteretic shifts of the gate voltage characteristics. We demonstrate the tuning of pinch-off voltages in quantum dot devices over hundreds of millivolts that then remain stable at least for hours. Applying our method, we homogenize the pinch-off voltages of the plunger gates in a linear array for four quantum dots, reducing the spread in pinch-off voltages by one order of magnitude. This work provides a new tool for the tuning of quantum dot devices and offers new perspectives for the implementation of scalable spin qubit arrays.

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Semiconductor spin qubits have gained increasing attention as a possible platform to host a fault-tolerant quantum computer. First demonstrations of spin qubit arrays have been shown in a wide variety of semiconductor materials. The highest performance for spin qubit logic has been realized in silicon, but scaling silicon quantum dot arrays in two dimensions has proven to be challenging. By taking advantage of high-quality heterostructures and carefully designed gate patterns, we are able to form a tunnel coupled 2 × 2 quantum dot array in a ²⁸Si/SiGe heterostructure. We are able to load a single electron in all four quantum dots, thus reaching the (1,1,1,1) charge state. Furthermore, we characterize and control the tunnel coupling between all pairs of dots by measuring polarization lines over a wide range of barrier gate voltages. Tunnel couplings can be tuned from about 30 μ eV up to approximately 400 μ eV . These experiments provide insightful information on how to design 2D quantum dot arrays and constitute a first step toward the operation of spin qubits in ²⁸Si/SiGe quantum dots in two dimensions.

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