Electrostatic uniformity and two-dimensional quantum dot arrays in silicon and germanium

Abstract

The spin of a single electron or hole provides an attractive candidate for implementing a quantum bit when confined in a semiconductor quantum dot. Such a spin qubit is characterized by long coherence and short gate times. High-fidelity single and two-qubit operations have been demonstrated as well. Additionally, semiconductor quantum dots have a small footprint (~ 100 nm x 100 nm) and their fabrication employs techniques similar to processes commonly used in modern semiconductor technology foundries. This promises the realization of dense qubit arrays, leverage through industrial fabrication, and direct co-integration with classical control circuits.

Thus far, one-dimensional quantum dot arrays have been studied extensively. Yet, only by realizing two-dimensional quantum dot arrays the small footprint of quantum dots is fully exploited. Also, due to their small size quantum dots are extremely sensitive to their local environment and fabrication imperfections. In current devices, an individually tailored set of gate electrode voltages is required for each quantum dot to confine a single charge. The limited space available for routing these voltages on the device, coupled with the associated overhead in required voltage sources, presents a challenge in scaling quantum dot arrays, especially two-dimensional arrays.

This thesis focuses on two-dimensional quantum dot arrays and gate voltage uniformity. The first part (chapter 3 and 4) reports the realization of two-dimensional quantum dot arrays in a silicon/silicon-germanium (Si/SiGe) and a germanium/silicon-germanium (Ge/SiGe) heterostructure. Afterward (chapter 5 and 6), a novel all-electric method is presented to achieve increased homogeneity of the required gate voltages.

In chapter 3 a 2 x 2 quantum dot array in a Si/SiGe heterostructure is presented. It is tuned to be occupied by a single electron per quantum dot reaching the (1,1,1,1) charge state. Dedicated barrier gate electrodes on the device allow for controlling the interdot tunnel couplings between neighbouring quantum dots from about 30 ueV up to approximately 400 ueV as characterized through polarization line measurements.

In chapter 4 the focus is shifted towards a more scalable gate architecture for two-dimensional quantum dot arrays. It is inspired by random access architectures that are found in classical electronics. Specifically, a 4 x 4 quantum dot array in a Ge/SiGe heterostructure with shared gate electrode voltages is introduced. In this device, an odd charge occupancy is reached with either one or three holes in all 16 quantum dots simultaneously. Also, two shared barrier gate electrodes are placed between adjacent quantum dots. These enable selective control of the interdot tunnel coupling from less than 3 GHz to more than 10 GHz.

Spatial fluctuations in the electric background potential still limit the scalability of such a shared control array. Therefore, chapter 5 introduces a new method to increase the electrical uniformity in quantum dot devices. The presented method is based on applying stress voltages to the device gate electrodes. It enables the tuning of pinch-off voltages in quantum dot devices over hundreds of millivolts. Afterward, the new pinch-off voltages remain stable for hours at least. The method is used to homogenize the pinch-off voltages of the plunger gates in a linear array designed for four quantum dots. It reduces their spread by one order of magnitude from 153 mV to 20 mV.

Motivated by this demonstration, in the experiment presented in chapter 6 the stress voltage tuning method is applied to control the plunger gate voltages required to reach single electron occupation in a quantum dot array. In a double quantum dot, a stable (1,1) charge state is reached at identical and predetermined plunger gate voltage and for various interdot couplings. Finally, by applying stress voltages a 2 x 2 quantum dot array is tuned such that the (1,1,1,1) charge state is reached when all plunger gates are set to 1 V.