Superconducting qubits are a leading platform holding potential for realization of fault-tolerant universal quantum computation. However, experimental demonstration of quantum fault tolerance may require scaling up to hundreds of physical qubits (Chapter 1).

The non-linearity of superconducting qubits emerges from current-phase relation in superconducting tunnel junctions, better known as Josephson junctions (Chapter 2). The transmon is a special case of the charge qubit with a large parallel shunt capacitance which results in suppression of charge noise sensitivity at the cost of reduced anharmonicity. The resonance frequency of a transmon depends on the charging energy contributed by the total capacitance of the circuit and the non-linear inductive energy of a Josephson junction. This inductance is in turn directly proportional to the room-temperature conductance of the tunnel junctions, determined by the junction area and thickness of the tunnel barrier. The manipulation of superconducting artificial atoms by strongly coupling to microwave photons is achieved using circuit quantum electrodynamics. In planar superconducting circuits, on­-chip transmission lines based on coplanar waveguide geometry is routinely employed to manipulate and readout the qubit states (Chapter 3).

The QuSurf architecture for a full-stack quantum computer features an extensible surface code comprising flux-tunable qubits with four-port connectivity to nearest neighbours. The first distance-3 logical qubit requires a 2D lattice of 17 qubits to perform quantum error correction. At the hardware level, we concurrently pursue a short-term low-overhead and a long-term high-overhead strategy with lateral and vertical input/output signal routing respectively (Chapter 3). The usefulness of a superconducting quantum processor depends on three main fabrication metrics, the physical yield of individual components, how well it matches the chip design specifications and its susceptibility to environmentally-induced decoherence (Chapter 4). Due to the nanometer-scale of Josephson junctions, it is particularly challenging to reliably target a desired qubit frequency within a margin of 50 MHz.

This thesis outlines the current fabrication bottlenecks which limit scalability with a focus on increasing the precision of qubit frequency targeting. The addition of through-silicon vias for vertical routing of signals and increasing the density of on-chip components add layers of complexity to this problem, which necessitates testing two variants of Josephson junctions with subtle differences in the fabrication process and its geometry. The primary objective is to systematically identify and quantify the sources of deviation affecting fabrication of the two Josephson junctions variants. To determine the causes of spread in Josephson junctions aside from intrinsic variations in the tunnel barrier, room-temperature conductance measurements are compared for thousands of test junction structures fabricated at waferscale. (Chapter 5). We also develop customized fabrication tools and techniques to achieve selective or global tailoring of qubit frequencies (Chapter 6). The thesis concludes with a summary on the factors identified in this work which impacts qubit frequency targeting, a reflection on the limitations of this work and an outlook on specific aspects of scalability of superconducting qubits in the near future (Chapter 7). @en

We investigate die-level and wafer-scale uniformity of Dolan-bridge and bridgeless Manhattan-style Josephson junctions, using multiple substrates with and without through-silicon vias (TSVs). Dolan junctions fabricated on planar substrates have the highest yield and lowest room-temperature conductance spread, equivalent to ∼ 100 M H z in transmon frequency. In TSV-integrated substrates, Dolan junctions suffer most in both yield and disorder, making Manhattan junctions preferable. Manhattan junctions show pronounced conductance decrease from wafer center to edge, which we qualitatively capture using a geometric model of spatially-dependent resist shadowing during junction electrode evaporation. Analysis of actual junction overlap areas using scanning electron micrographs supports the model, and further points to a remnant spatial dependence possibly due to contact resistance.

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We present the use of a set of airbridges to trim the frequency of microwave coplanar-waveguide (CPW) resonators post-fabrication. This method is compatible with the fabrication steps of conventional CPW airbridges and crossovers and increases device yield by allowing compensation of design and fabrication uncertainty with 100 MHz range and 10 MHz resolution. We showcase two applications in circuit QED. The first is the elimination of frequency collisions between resonators intended to readout different transmons by frequency-division multiplexing. The second is frequency matching of readout and Purcell-filter resonator pairs. Combining this matching with transmon frequency trimming by laser annealing reliably achieves fast and high-fidelity readout across 17-transmon quantum processors.

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Artificial neural networks are becoming an integral part of digital solutions to complex problems. However, employing neural networks on quantum processors faces challenges related to the implementation of non-linear functions using quantum circuits. In this paper, we use repeat-until-success circuits enabled by real-time control-flow feedback to realize quantum neurons with non-linear activation functions. These neurons constitute elementary building blocks that can be arranged in a variety of layouts to carry out deep learning tasks quantum coherently. As an example, we construct a minimal feedforward quantum neural network capable of learning all 2-to-1-bit Boolean functions by optimization of network activation parameters within the supervised-learning paradigm. This model is shown to perform non-linear classification and effectively learns from multiple copies of a single training state consisting of the maximal superposition of all inputs.

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Minimizing leakage from computational states is a challenge when using many-level systems like superconducting quantum circuits as qubits. We realize and extend the quantum-hardware-efficient, all-microwave leakage reduction unit (LRU) for transmons in a circuit QED architecture proposed by Battistel et al. This LRU effectively reduces leakage in the second- and third-excited transmon states with up to 99% efficacy in 220 ns, with minimum impact on the qubit subspace. As a first application in the context of quantum error correction, we show how multiple simultaneous LRUs can reduce the error detection rate and suppress leakage buildup within 1% in data and ancilla qubits over 50 cycles of a weight-2 stabilizer measurement.

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Future fault-tolerant quantum computers will require storing and processing quantum data in logical qubits. Here we realize a suite of logical operations on a distance-2 surface code qubit built from seven physical qubits and stabilized using repeated error-detection cycles. Logical operations include initialization into arbitrary states, measurement in the cardinal bases of the Bloch sphere and a universal set of single-qubit gates. For each type of operation, we observe higher performance for fault-tolerant variants over non-fault-tolerant variants, and quantify the difference. In particular, we demonstrate process tomography of logical gates, using the notion of a logical Pauli transfer matrix. This integration of high-fidelity logical operations with a scalable scheme for repeated stabilization is a milestone on the road to quantum error correction with higher-distance superconducting surface codes.

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Simple tuneup of fast two-qubit gates is essential for the scaling of quantum processors. We introduce the sudden variant (SNZ) of the net zero scheme realizing controlled-Z (CZ) gates by flux control of transmon frequency. SNZ CZ gates realized in a multitransmon processor operate at the speed limit of transverse coupling between computational and noncomputational states by maximizing intermediate leakage. Beyond speed, the key advantage of SNZ is tuneup simplicity, owing to the regular structure of conditional phase and leakage as a function of two control parameters. SNZ is compatible with scalable schemes for quantum error correction and adaptable to generalized conditional-phase gates useful in intermediate-scale applications.

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The preparation of thermal equilibrium states is important for the simulation of condensed matter and cosmology systems using a quantum computer. We present a method to prepare such mixed states with unitary operators and demonstrate this technique experimentally using a gate-based quantum processor. Our method targets the generation of thermofield double states using a hybrid quantum-classical variational approach motivated by quantum-approximate optimization algorithms, without prior calculation of optimal variational parameters by numerical simulation. The fidelity of generated states to the thermal-equilibrium state smoothly varies from 99 to 75% between infinite and near-zero simulated temperature, in quantitative agreement with numerical simulations of the noisy quantum processor with error parameters drawn from experiment.

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Protecting quantum information from errors is essential for large-scale quantum computation. Quantum error correction (QEC) encodes information in entangled states of many qubits and performs parity measurements to identify errors without destroying the encoded information. However, traditional QEC cannot handle leakage from the qubit computational space. Leakage affects leading experimental platforms, based on trapped ions and superconducting circuits, which use effective qubits within many-level physical systems. We investigate how two-transmon entangled states evolve under repeated parity measurements and demonstrate the use of hidden Markov models to detect leakage using only the record of parity measurement outcomes required for QEC. We show the stabilization of Bell states over up to 26 parity measurements by mitigating leakage using postselection and correcting qubit errors using Pauli-frame transformations. Our leakage identification method is computationally efficient and thus compatible with real-time leakage tracking and correction in larger quantum processors.

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Variational quantum eigensolvers offer a small-scale testbed to demonstrate the performance of error mitigation techniques with low experimental overhead. We present successful error mitigation by applying the recently proposed symmetry verification technique to the experimental estimation of the ground-state energy and ground state of the hydrogen molecule. A finely adjustable exchange interaction between two qubits in a circuit QED processor efficiently prepares variational ansatz states in the single-excitation subspace respecting the parity symmetry of the qubit-mapped Hamiltonian. Symmetry verification improves the energy and state estimates by mitigating the effects of qubit relaxation and residual qubit excitation, which violate the symmetry. A full-density-matrix simulation matching the experiment dissects the contribution of these mechanisms from other calibrated error sources. Enforcing positivity of the measured density matrix via scalable convex optimization correlates the energy and state estimate improvements when using symmetry verification, with interesting implications for determining system properties beyond the ground-state energy.

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Conditional-phase (cz) gates in transmons can be realized by flux pulsing computational states towards resonance with noncomputational ones. We present a 40 ns cz gate based on a bipolar flux pulse suppressing leakage (0.1%) by interference and approaching the speed limit set by exchange coupling. This pulse harnesses a built-in echo to enhance fidelity (99.1%) and is robust to long-timescale distortion in the flux-control line, ensuring repeatability. Numerical simulations matching experiment show that fidelity is limited by high-frequency dephasing and leakage by short-timescale distortion.

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We present a method to fabricate insulated gold mechanically controlled break junctions (MCBJ) by coating the metal with a thin layer of aluminum oxide using plasma enhanced atomic layer deposition. The Al₂O₃ thickness deposited on the MCBJ devices was varied from 2 to 15 nm to test the suppression of leakage currents in deionized water and phosphate buffered saline. Junctions coated with a 15 nm thick oxide layer yielded atomically sharp electrodes and negligible conductance counts in the range of 1 to 10^-4 G₀ (1 G₀ = 77 μS), where single-molecule conductances are commonly observed. The insulated devices were used to measure the conductance of an amphiphilic oligophenylene ethynylene derivative in deionized water.

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