One of the main components used in superconducting quantum chips is the Josephson junction. Currently when fabricating Josephson junctions, the resistance uniformity at wafer-scale is not optimal. It is also known that an annealing process can alter the junction resistance and with it the qubit frequency. However, laser annealing has only shown to be able to increase the junction resistance. An equally effective and minimally invasive technique to decrease junction resistance is necessary to have full control on frequency
targeting. Thermal annealing in a reducing environment is known to result in a global decrease in junction resistance. To get better control on frequency targeting the techniques could be combined. A die containing not-capped Manhattan type Josephson junctions has been annealed using forming gas at 200°C for 2 minutes, based on a non-linear least squares reciprocal function fit to the data an asymptotic lower bound of 467 μSμm^-2 for the change in conductance per unit area has been found. Smaller junctions with an area
of approximately 0.03 μm² undergo a bigger change in conductance per unit area of around 800 μSμm^-2. Annealing at higher temperatures such as 300 and 400°C results in a decrease of the conductance. There is no substantial change in yield of usable SQUIDs when using a rapid thermal annealing process.

This report introduces a customized software tool to enable automation of optical inspection optical and SEM images of a superconducting quantum processor during its fabrication. This is achieved by implementing image processing algorithms using the Python package OpenCV. This suite consist of three components; pyclq_base, pyclq_jj, pyclq_ab. The first component will template match the base layer to its CAD design. The second component will be a validation for the airbridges. These have 3D components and therefore can not be matched to their CAD design. The results had about twice as many false positives for, broken bridges, and no false negatives. The third component measures the width and overlap area for Manhattanstyle Josephson junctions using two different filtering methods; k-mean segmentation and thresholding. The results of these three components are used as a tool to understand the sources of spread in the conductance of Josephson junctions therefore optimizing the fabrication process.

In this thesis variations in the Josephson junction conductance across a 100 mm wafer are studied. For this study junctions fabricated with a Dolan bridge and with the Manhattan layout are used. These junctions are fabricated on a planar and a non-planar NbTiN base layer to characterise the uniformity. On a planar
base junctions fabricated with a Dolan bridge showed higher uniformity and yield than junctions with the Manhattan layout. On a non-planer base junctions fabricated with a Manhattan layout showed a higher uniformity
than the Dolan bridge junctions. This can be attributed to the through silicon vias, which affect the resist spinning required for the Dolan bridge.
Manhattan style junctions are fabricated on a Si base layer in an attempt to improve the uniformity across a 100 mm wafer. By fabricating junctions on Si overall fabrication complexity is reduced, while also reducing the fabrication time. These junctions are used to investigate the role of oxygen ashing prior to the junction deposition. We find that the ashing increase the uniformity of the junctions, however, further attempts to improve the uniformity using different ashing steps did not how any additional improvements. Finally, to explain the variations in Manhattan style junctions a geometric model is introduced. This model is based on the thickness of the top resist stack, which could potentially affect the width of the junction electrodes. The model is compared with SEM images and with the coefficient of variation. The model shows correspondence with the SEM data, but overestimates the variations when compared with the coefficient of variation.