Neuromorphic computing, a novel computing configuration inspired by the brain, aims to perform calculations based on physical neurons and synapses, attracting significant attention in recent years. Resistive random access memory (RRAM) shows great potential in this field, demonstrating high operation speed, nanoscale scalability, long retention time, non-volatile performance, and a simple structure.

Despite the promising performance of RRAM, a high forming voltage potentially hinders the widespread application of the device. This thesis aims to diminish and eliminate the forming voltage. To achieve this, different metals were inserted between the insulator layer and the bottom electrode of the RRAM, serving as an interface metal layer. The interface metal was expected to introduce oxygen vacancies to the insulator, thereby decreasing the forming voltage. Advanced nanofabrication processes were employed in the cleanroom, and a related recipe was developed. The influence of layer thickness and device area was also studied to gain a comprehensive understanding. Among all the samples, Ru-based devices were observed to be forming-free.

Data analysis methods were applied to model the data, with the random forest method found to be the most suitable, achieving an accuracy of 82.4%. The model was verified by measurements of 10 nm Ru-based devices. Feature importance was then calculated to interpret the model. The four most important features determining the forming voltage are the thickness, standard electrode potential, area, and work function of the interface metal. This work adopts a new approach to eliminating the forming voltage, not only providing a forming-free device but also offering a guideline for future research on forming voltage.

Quantum computing promises revolutionary advancements in computational power by leveraging quantum mechanical phenomena such as superposition and entanglement. Diamond color centers have emerged as promising candidates for quantum information processing due to their long coherence times and scalability. Photonic integrated circuits (PICs), represent a mature technology that facilitates on-chip quantum operations in a compact and scalable manner. In quantum applications, PICs play a crucial role in routing and manipulating quantum information.

The transition to the "More than Moore era," following the plateauing of Moore's law, has highlighted the importance of MEMS (Micro-Electro-Mechanical Systems) technology for continued advancements in electronics. Integrating MEMS with PICs and quantum applications, due to its high performance and mass production capabilities, offers a promising avenue for large-scale device integration and multi-qubit systems.

Designing photonic devices for integration with diamond color-center qubits presents several challenges. Primarily, designing photonic devices for the visible spectrum involves challenges related to device feature sizes approaching the limits of fabrication resolution. Additional challenges include ensuring scalability in quantum computing and compatibility with complementary metal-oxide semiconductor (CMOS) electronics. This requires devices that operate with low power consumption, low actuation voltage, and minimal crosstalk, necessitating significant optimization of MEMS components. Furthermore, integrating MEMS devices demands careful consideration of the mechanical properties of the materials and the designed structures.

This project discusses the design, fabrication, and characterization of a photonic directional coupler for use in beamsplitter and optical MEMS switch configurations in the visible spectrum. The photonic beamsplitter is essential for the controlled manipulation of quantum states, crucial for executing quantum algorithms. The optical MEMS switch provides dynamic control over optical pathways, leveraging the advantages of photonics and MEMS technology. The goal of this project is to optimize the directional coupler design for footprint, and fabrication accuracy, and to propose a directional coupler-based optical MEMS switch design that features low actuation voltage and high extinction ratio. Additionally, this project aims to establish the process recipes for fabricating the designed directional couplers and MEMS components, with particular attention to the physical resolution of small feature sizes, and to evaluate the extent to which the designed performance is achieved. By addressing these topics, the project aims to contribute to the large-scale integration of diamond color center qubits for quantum computing applications.

Demand for high density, high bandwidth, and low power Integrated Circuits (ICs) is rapidly increasing even as Moore's Law is starting to plateau. Among the new wave of technologies that are meant to continue the prevalent trend of semiconductor device scaling, 3D System Integration promises many advantages over traditional single-planar designs. This technology enables designers to stack multiple dies and unlock new functionality by reducing the footprint of the final device package. Using 3D Integration, multiple different types of chiplets (Digital IC, Analog IC, MEMS) can be integrated into a single package, potentially bypassing an expensive move to a newer process node and unlocking even more functionality from the same package.

These downscaling issues are not limited to traditional CMOS technologies but extend to Quantum Computers. Due to the highly heterogeneous nature of Quantum ICs, and especially their requirement of low qubit decoherence noise, we require high-density connections from the Qubit layer to the Microelectronics Control layer while maintaining appropriate spacial separation between the two. In this project, the qubit layer is comprised of Diamond Colour Centers in a Photonic IC with other optical components such as SNSPDs, and MEMS switches. On the other hand, the microelectronics control layer is a Cryogenic CMOS chip.

The main goal of this project is to design an Interposer and related technologies like Through Silicon Vias (TSVs) and Microbumps to successfully integrate these two chiplets in a single 3D assembly. We conduct thermal analysis of multiple 3D assembly designs using Finite Element Modelling to derive optimum fabrication specifications. Subsequently, fabrication recipes are developed and optimised for TSV etching, coating, and patterning with superconductive sidewall liners. Recipes are also developed to fabricate Indium Microbumps using techniques like evaporation, liftoff, and atmospheric reflow. Utilizing these microbumps, we conduct cold-compression flip-chip experiments. Finally, we establish cryogenic measurement setups to electrically characterize these fabricated devices.

In this Bachelor graduation project, a 16x16 Single Photon Avalanche Diode (SPAD) array is designed in 40nm TSMC CMOS for diamond single Nitrogen Vacancy center array readout. It includes an active quenching and recharge circuit (AQC), a hold-off circuit for controllable dead-time and IO electronics for off-chip communication. The chip is part of a proposed high sensitivity magnetometer based on single NV center readout with a focus on detecting cancer in biological samples. From the Quantum Integration Technology (QIT) lab, pre-designed SPADs were received to be implemented into the design together with SPAD quenching, recharge and input-output controller electronics. A SPAD model is adapted from literature for simulations of the electric behaviour of the electronics. We present a design and implementation of the Active Quenching Circuit (AQC), a design and implementation of the recharge and hold-off circuits, Input-Output (IO) interface design and implementation and the final top-level implementation ready for the next tape out. Post-layout simulations show negligible speed slowdown and distortion. The AQC has a 12ns quenching time and a 1ns recharge time, leading to a theoretical maximum count rate of 76Mc/s. The hold-off circuit has a tunable dead-time for afterpulsing reduction and 16, 16 bit parallel-in-serial-out (PISO) modules allow per-row readout of the array. The electronics are co-located with the SPADs and pixel pitch is 24m. The final chip design meets the single NV fluorescence count rate requirement of above 3 Mc/s, the 1.1x1.1 ZZ2 area requirement, the 32-pin IO requirement, the 16x16 SPAD pixel requirement and, steps have been taken to ensure acceptable crosstalk levels in the array. Finally, the SPAD array chip is designed to run on a 1GHz clock. It should interface with an FPGA that configures the hold-off circuit and reads out the SPAD status bits.

Quantum sensing technology has emerged as a promising field with superior sensitivity and accuracy in magnetic field sensing compared to conventional technologies. This breakthrough offers significant prospects in the biomedical sector, particularly in the realm of medical imaging.

This project focuses on the implementation of quantum sensing using an array of single Nitrogen Vacancy (NV) centers combined with an array of Single Photon Avalanche Diodes (SPADs). SPADs are available in various technologies and forms. To identify the optimal SPAD for this specific application, different SPADs with diverse parameters are designed on a chip using standard 40 nm TSMC process. These parameters include active area, active area shape and metal shielding.

The research aims to validate and characterize the performance of these distinct SPADs. However, during the validation tests, it was observed that the SPADs did not meet the criteria. The presence of ESD diodes on the chip introduced a low resistance current path, thereby hindering the characterisation process of the SPADs. Solutions to fix this problem and improve the system are provided.

The documented validation methods include general chip testing, establishing the I-V curves of the SPADs and avalanche and quenching testing. In addition, the characterisation methods for junction capacitance, dark count rate (DCR), photon detection probability (PDP) and time jitter are given.

For characterizing DCR and PDP a readout system is designed. It consists of an analog-to-digital converter (ADC), FPGA and Arduino. The data is communicated continuously to a PC. The ADC is not fully tested. On the other hand, the FPGA and Arduino are tested and verified to be sufficient for the DCR measurements. The readout system is too inaccurate for PDP measurements. A recommendation on how to make the readout system sufficient for PDP is given.

Diamond color centers have been increasingly gaining attention in research due to their desirable optical properties that make them suitable for applications such as quantum computing, quantum sensing and quantum communication. However, the main challenge has been on-chip integration of diamond color centers with high scalability and high yield. Many diamond integration methods have been researched, such as heterogeneous wafer bonding of diamond-on-insulator photonics. While this method offers high scalability and wafer level fabrication, optical performance is not guaranteed due to the non-ideal processing which results in lower yield. Another integration method is pick and place, which demonstrated high yield as the diamond color centers can be pre-selected before integration, and thus resulting in higher yield. Here, pick and place integration of diamond nano-photonic structures is presented. For that purpose, an adiabatic coupler is designed, with simulation results showing 0.36 dB insertion loss and 3dB misalignment tolerance of 180 nm and 5 um in x and z directions respectively. A mechanical support structure is designed such that optical losses at that interface are minimized. The simulated loss is reduced from 33 % to only 4 % and the cross-talk is -11 dB. Further optical measurement is needed to determine the achieved transmission of the integrated diamond chiplets. Finally, pick and place is performed with 6 different supporting structure designs. The yield is 25 % with minimum misalignment of 50 nm which is mainly dominated by random motion of the diamond chiplet as it gets closer to the receptor chip. This random motion is attributed to the surface roughness of the receptor chip and and lower surface of the diamond chiplet. In addition, residual charges in both chips results in Coulomb forces acting on the diamond chiplet and thus contributing to the misalignment. It is expected that the magnitude of the random motion, and consequently, the misalignment, will be improved by treating the receptor chip surface with HMDS and de-ionizing both the diamond chiplet and the receptor chip.

Classical computer have difficulties simulating specific complex problems, therefore other computation options are being explored. One of these options is the quantum computer, which is expected to excel in various industries. The challenge for the quantum computer is scaling it up to a high number of qubits. The diamond-based quantum computer is a suitable candidate for quantum computer, because it can be made scalable, with long coherence times, relatively high temperatures and low cross talk. Making such a scalable modular quantum computer using diamond qubits requires heterogeneous integration of optical components. Multiple integrations techniques for optical components exist, however in this thesis we are particularly interested in integrating a superconducting nanowire single photon detector (SNSPD) with pick & place onto the quantum chip to read out the photons emitted by diamond color-centers. The main goal of this thesis is to find out which integration scheme leads to the highest on-chip detection efficiency of a pick & place on waveguide integrated SNSPD.

In this work we designed a silicon nitride structure with low loss tapered support structures. Next different releasing methods are introduced to release the fabricated silicon nitride structure independent of the material stack and with a high yield. Lastly, we show how waveguide structures can be pick & placed on receptor chips that underwent surface treatment.

Color centers in diamond offer exciting opportunities for implementing an effective solid-state spinphoton interface. Access to and control of spin-photon interaction can help realize a scalable, modular quantum computer using the color center spins. A large magnetic field is needed for splitting the color center spin states, enabling definition of the qubits. In addition to the large, global magnetic field (∼1T), applying a small and tunable magnetic field (order of mT) in the vicinity of individual color centers is advantageous as it allows for external field inhomogeneity compensation and multiplexing of the qubit driving frequency. Local tuning of the magnetic field magnitude might be achieved by driving DC currents through microscopic coils located in close proximity of the respective color centers. Since the systems must be located at cryogenic temperatures, cooling power is limited. Superconducting coils are therefore considered for local tuning instead of conventional metal. Design requirements for the local tuning coils depend strongly on design choices of the external magnet, externally applied field magnitude, number of FDM channels and coil distance from the color center. In order to find a design process that easily accounts for changes in these choices, the utilization of FEM physics simulations is studied. Two simulation methods are considered and tested in COMSOL Multiphysics. The first method is called 𝐻-𝜙-formulation, which is considered for optimizing the coil geometry. This method is based on a classical description of superconductivity and is shown here to have potential for simulating large coil structures. The second method allows for 3D simulation of superconductors based on the time-dependent Ginzburg-Landau (TDGL) equations. This method is considered with the goal of predicting changes in critical current density due to differences in cross-section dimensions. It is shown that this method can qualitatively reproduce transport characteristics of microscopic wires when no magnetic field is applied. When a magnetic field is applied, the observed vortex dynamics and resistivity correspond to that of material with no impurities or defects. Adding impurities in the form of geometrical deformations is shown here to be possible. However, further development on the method is required in order to overcome computational limitations and to determine unknown factors such as the impurity density and pinning forces. Until such time, the design procedure recommended in this thesis is based on 𝐻-𝜙-formulation simulations in combination with measurements of straight transport lines for critical current density characterization. Fabrication of NbTiN films is successfully tested by patterning coil-shaped structures, followed by DC magnetron sputtering and liftoff. The coil structures will be used to measure deviations from the expected critical current density due to geometry and to validate the recommended design procedure. Straight lines NbTiN geometries are fabricated with the purpose of finding the critical current density as a function of cross-section dimensions and magnetic field. These samples will be used to select the cross-section dimensions that deliver optimal critical current density, which will consequently be used in simulation to optimize the geometry.

Modular quantum computer chip based on spin qubits in diamond will enable an increased connectivity, a high fidelity, and a low error-rate when the number of qubits increases. The high-quality diamond substrates have the maximum size in the order of mm2, preventing use of advanced semiconductor manufacturing line. Therefore, for a large-scale integration of qubits, there is a need for a wafer-scale diamond for scalable nanofabrication. Here, diamond-on-insulator structure will enable self-standing diamond structure by under-etching the insulator. Hydrophilic direct bonding of single crystalline diamond substrate on silicon is a promising approach.

In this research, a process is developed and optimized for hydrophilic direct bonding of (100)-oriented diamond on a low-temperature deposited SiO2 on silicon substrate. The process condition involves treating a (100) CVD diamond substrate in a Piranha solution. A 300-nm-thick SiO2 is PECVD deposited on a (100) silicon wafer which afterwards undergoes a surface activation process by oxygen plasma. The two substrates were contacted in an ambient without applying pressure, cooled, and then annealed. It should be noted that there was no pressure applied during the annealing. By die shear testing, a strong shear strength was measured and further elongating the Piranha cleaning time provided more shear strength bonding.

This project aims to develop a compact and affordable mobile prototype of a Quantum Random Number Generator (QRNG) utilizing the inherently random quantum effect of photons. The system is built exclusively with off-the-shelf components to make it accessible to new user groups who find existing QRNGs too expensive and complex.

This report focuses on the design and implementation of both a detection system and an enclosure, which are designed to be used in a quantum random number generator. These parts are designed to be manufactured using off-the-shelf components to make the quantum random number generator affordable and accessible to a completely new user-group that cannot afford and operate the currently existing alternatives for quantum random number generation. After implementing the designed systems it is found that although the output of the system is random, true-randomness cannot be guaranteed using off the shelf components, because of the interference of classical noise sources.

Over the past few years, post-surgery monitoring has become an important aspect of the patient’s healthcare in the modern clinical medicine. This kind of monitoring is done to examine various physical and chemical parameters, while considering any post-surgery complications. Therefore, the patient’s care is continued even after the surgical treatment and any sudden complications can be prevented from this intensive monitoring. For this purpose, electronic implantable sensors are preferred to monitor the various required physiological factors such as blood pressure, body temperature, heart rate, etc. This kind of in-vivo measurements can be done by directly implanting the sensors at the afflicted site inside the patient’s body. Therefore, the implantable biosensors are commonly used to monitor and measure various parameters such as pressure, stress and strain, pH, and many others in a less invasive way.
As the implantable biosensors are directly placed on the tissue or organ for monitoring, the efficiency of sensing and mapping the required information can be achieved by maximal surface contact. This can be fulfilled with the help of the wide range of available flexible and stretchable materials such as polyimide, PDMS, and many more. Instead of the conventional IC fabrication process, printing technology is a better alternative to fabricate these flexible and stretchable biosensors at low cost with a great amount of substrate choices. Among the available semiconducting inks, liquid silicon proved to be a better choice in making devices with good performance. The term ‘liquid silicon’ refers to silicon-based polymers such as Polysilanes. Thus, the combination of liquid silicon based implantable biosensors on flexible and stretchable substrates has lot of potential to be explored.
In this thesis, the focus is to print a conductive polysilicon layer on a flexible and stretchable substrate. Initially, the substrate materials- Polyimide and PDMS are chosen as per the requirements of flexibility, stretchability, biocompatibility and mechanical stability. After the preparing the substrate, the liquid silicon is coated on top of the substrate and the wettability is adjusted during the coating with the help of UV light. This polysilane layer is crystallised using KrF excimer laser to form a polysilicon layer. Thus, the polysilicon layer of thickness of about 200 nm is formed on top of a flexible and stretchable substrate.
This work forms the basis for future work in which the polysilicon resistors can be fabricated to be used as piezoresistive strain sensors. It can be further explored to include other functionalities such as real-time monitoring and self-sufficient in terms of power, etc. The choice of materials can be further expanded to include bio-resorbable materials such as silk, gelatin, and many more.

3-D chip integration is considered to be the best way for further increasing the number of qubits on chip, and also for integration of qubits and readout electronics. Works have been done to stack two wafers with superconductive interconnections as a demonstration for feasibility of 3-D qubit integration.But all of them use an extra layer of adhesives, indium in particular, to join two neighboring planes.Indium is a good choice of adhesive for wafer bonding at cryogenic temperature. However, there are potential issues to employ this extra layer of adhesive. First, the critical temperature (Tc) of indium being 3.4K means it is suitable preferably for superconducting qubits, but not good enough for qubit implementations or other cryogenic that have above-4K expectations. Second, one general problem in wafer bonding is that alignment is not accurate. Adding an extra layer of anything increases the degree of misalignment. In this work, the extra adhesive layer is abandoned and two wafers are bonded by direct-bonding technique. First, niobium nitride (NbN) is chosen to be the skeleton for this 3-D structure due to its high Tc (18K) as well as its simple composition hence easy fabrication. Sputtering is the method used to fabricate such metal nitride. Sample with Tc=15.6K has been measured so far. Second, both wafer-scale and miniaturized pattern are designed to measure contact resistance of direct bonding of NbN films in room and cryogenic temperature. This work shows the potential of direct-wafer bonding in 3-D chip integration at cryogenic environment, and could further lead to scaling up of quantum processors.

Silicon accelerometers used in the automotive industry should be improved in resolution and accuracy. Exploiting quantum effects in diamond to improve sensing accuracy is a popular technique for nanoscale sensing applications. This thesis will present a new design concept for an accelerometer using these quantum effects for sensing on a macroscopic scale. This sensor can sense these forces with a resolution of 6g and a range of 120g. In measurement time it is slower than current sensors, but our sensor can still serve as a prototype to be improved in the future.

The goal of this master thesis was to optimize the tunnel oxide passivating contact (TOPCon) concept for p-type substrates and implementation in silicon (Si) solar cells. TOPCon and other passivating contacts are believed to be a crucial link for increasing solar cell efficiency and further reducing the costs of photovoltaic (PV) systems. The concept that comes closest to the theoretical Auger limit is the Si heterojunction cell with a record efficiency of 26.6%[1]. A problem with this type of cells is that the process temperature that is allowed is limited, increasing the processing temperature results in decreasing passivation and thus loss of efficiency. The TOPCon concept can withstand higher processing temperatures, which is beneficial when it comes to applying a transparent conductive oxide (TCO) layer of certain metallization schemes. For n-TOPCon good results have been obtained in the past leading to a record efficiency of 25.7%[2]. For p-TOPCon, the efficiency is significantly lower and the cause of this discrepancy is not fully understood yet. In this work, the boron doped TOPCon configuration was optimized by optimizing all of the individual components of this passivating contact concept. During this work the tunnel oxide, which can be grown using variousmethods, proved essential to obtain a good passivation. A comparison was made between four different growth methods for the tunnel oxide, from which it was concluded that the thermally grown tunnel oxide performed best in terms of passivation quality and thermal stability. The optimal p-TOPCon stack was found to consist of three layers: a thin intrinsic hydrogenated amorphous silicon (a-Si:H) layer, followed by a boron doped a-Si:H layer. The p-TOPCon stack is finalized by depositing a thin silicon carbide (SiC) capping layer, which was also boron doped. Besides passivation, the specific contact resistivity was also investigated. A metallization stack consisting of titanium, palladium, and silver proved to result in the lowest contact resistivity values. The lowest value which was measured was 10 m­cm2, this is below the threshold value for which fill factor (FF) losses are to be expected. Implementing a thin tungsten oxide (WOx) layer underneath this metallization stack resulted in a stark increase in the specific contact resistivity values. Furthermore, the tunnel oxide influenced the contact resistivity values, where a lower oxidation time and temperature resulted in lower contact resistivity values. In order to better understand the correlation between contact resistivity and passivation, the contact resistivity values and corresponding recombination current values were fitted to two different models: the oxide tunneling model [3] and the pinholes model [4]. The measured resistivity values all laid in the saturated regime, whichmade it difficult to exclude one of the two models. The passivation quality of the p-TOPCon stack was improved by altering the tunnel oxide to a thermally grown oxide and optimizing the TOPCon stack. This resulted in an implied open-circuit voltage (iVoc) value of 710 mV and an implied fill factor (iFF) value of 84.5 %. A good contact was obtained with a titanium, palladium, silver metallization. This resulted in a specific contact resistivity value of 10m­cm2.