Solder joint failure is one of the most common board-level failure modes in electronic components. It is crucial for a next-generation reliability assessment method to have an in-situ health monitoring system in place to evaluate the current state of degradation. This is achieved by specialized embedded sensors and processing the data on the edge. This study focuses on monitoring the mechanical degradation of package-to-PCB solder interconnects of a WLCSP using a high-resolution piezoresistive sensor. First, a measurement workflow was set up to optimize and significantly improve the sensor readout time. Then, utilizing a design of experiments, the test specimens were subjected to certain combinations of mechanical and thermal loads in a four-point bending setup. Temperature-coupled mechanical loading showed a greater impact on the resulting stress pattern compared to that of a superposition of the corresponding individual purely thermal and mechanical load configurations. Finally, the specimens were tested under a purely mechanical load until failure, and a correlation between the recorded stress pattern and the initiation and propagation of a crack was established.@en

SnAgCu solder joint has oligocrystalline (few large grains) structure and due to body-centered tetragonal (BCT) structure, each grain shows strongly anisotropic behavior. Modelling anisotropic behavior of grain scale solder joints has been extensively researched by this group. In this paper, anisotropic grain-scale plasticity model is used to predict variability of solder joint fatigue durability under sine sweep vibration excitation. Solder experiences different levels of cyclic stress for different grain orientations. Stress-based high cycle fatigue (HCF) model (Basquin’s model) and Miner’s rule are used for determining the variability of vibration durability of solder joints for different orientations and compared with experimental results.@en

Fan in and fan out wafer level packages are primarily used in the industry for applications in handheld consumer electronic products. The key benefits of wafer level package (WLP) are small form factor, reduced cost, improved electrical and thermal performance. WLP investigated in this study are directly surface mounted on PCB and have no intermediate substrate. Direct mount of package on PCB, leads to significant CTE mismatch between the package and board which stresses the package solder joint, leading to cyclic fatigue induced solder joint cracking. To overcome the solder joint cracking, stiffer solder alloys have been evaluated. However, higher stiffness of the solder alloy shifts the cyclic stress induced failure, from the solder joint to the package metal interconnect layers. Moreover, WLP on advanced silicon node have fragile low-k and extremely low-k back end of line dielectric layers that also crack or delaminate in cyclic fatigue. In this work extensive WLP platform development has been done with following DOE variables; multi-layer package routing, dielectric materials, die thickness, PCB design. Developed packages passed and outperformed the following product reliability qualification conditions - high temperature storage life (150°C, 1000 hours), highly accelerated stress test (110°C / 85%RH / Bias, 264 hours), component level temperature cycling (-55 °C to 125 °C, 1000 cycles), board level temperature cycling (-40 °C to 125 °C, 500 cycles) and board level drop test (1500g/0.5ms, 30 drops). Excellent reliability, functional performance, and successful chip package integration was achieved for WLP for crossover MCU products.

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Board level reliability can be of high interest for automotive electronic components when exposed to vibration-prone environments. However, the absence of an industry standard for board level vibration testing poses several challenges in establishing a well-characterized test setup. One of the challenges is that automotive applications can induce abnormal stresses on components that can lead to early failures in the field. Such loading conditions are not always covered in the current board level vibration test methods. This paper aims to correlate the stresses from automotive modules to board levels by measuring the printed circuit board (PCB) vibration spectrum. Firstly, the study compares and assesses several module board level vibration measurement units, such as LASER Doppler Vibrometer (LDV), strain gauges, and accelerometers. Experiments and simulations show that LDV enables good correlation with Micro-electro Mechanical Systems (MEMS) accelerometers. Secondly, the module-board interaction unveils insights into several module design features that impact the PCB vibration response and solder joint interconnect reliability. These findings underscore the necessity for the user to correctly validate the reliability of packages beyond board level testing, i.e., at the module level. This reliability test approach enables the translation of reliability test results from the lab to the field life of components once built in the final application equipment.

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Board level vibration testing is a commonly used method to predict the solder joint reliability of surface-mounted components seated onto printed circuit boards (PCB). Current board level vibration test methods are mainly developed from a solely mechanical stress application standpoint. This makes such stress tests one dimensional in nature and translation from experimentally obtained test results to the field life of components experiencing combined stress environments become ambiguous. This investigation provides insights to develop a highly accelerated vibration test approach to cover simultaneous vibration and temperature loading situations in the field. In this paper, test board layouts from the board level drop test method, JESD22-B111 (rectangular PCB), and JESD22-B111A (square PCB), prescribed by the Joint Electronic Device Engineering Council (JEDEC), are used to understand the combined stress applied to the solder interconnects. The evaluation process is carried out by means of simulations, supported by targeted experiments on ball grid array (BGA) packages with dimensions sizing from 12x12mm to 15x15mm. The results on rectangular test board assembly show reduced characteristic lifetime of solder joints when stressed under combined temperature-vibration test conditions. On the other hand, the square-shaped board type exhibits a different acceleration factor with a longer solder fatigue lifetime than that of the rectangular-shaped PCB type. Finite element simulation results complement well with this finding.

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Board level vibration testing is intended to assess prediction of the reliability of solder joint interconnects that are formed between electronic components and printed circuit boards (PCB). Frailties in the stress test experiment might lead to false board level reliability (BLR) evaluations. Therefore, it is essential to have a well-characterized board level vibration test method. Currently, there is no industrial test standard that prescribes board level vibration test method for electronic components at the PCB level. This paper examines the vibration test standards that are currently available in the industry and their applicability at the solder joint interconnect level. Next to that, it surveys the state-of-the-art board level vibration test setups and their impact on PCB dynamic loading and reliability at solder joint-PCB interface. It collates research on major building blocks of a board level vibration test method that includes vibration measurement techniques, PCB assemblies under test, board mounting schemes, operating environments, fault detection systems, and vibration test stress conditions that are currently used in the domain of solder joint level vibration testing. The findings from this paper are expected to reveal pitfalls and challenges while setting up board level vibration test experiments for electronic components. In addition, this paper attempts to identify research efforts that are required to make board level vibration testing a more credible means for assessing solder joint reliability. Outcomes from this study can further be used to guide future board level vibration specifications for electronic components.

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Board level vibration testing is an important characterization aspect that has to be considered during development and release of electronic components in applications involving harsh environments. Industrial reliability test standards prescribed by JEDEC recommend to stress a statistical representative sample size of at least 30 components. Consequently, the test execution time is undesirably long when testing all components sequentially. This paper provides a solution by developing a vibration test approach for simultaneously stressing multiple PCB assemblies. To start with, multiple boards are evaluated via vibrational spectrum analysis that is combined with a Finite Element Model (FEM) to calculate the strain at solder joint level. Limited variation is seen in calculated strain levels from PCB to PCB. This permits simultaneous testing of multiple PCB assemblies. Consequently, three test capacity expansion arrangements, namely One Dimensional (1D), Two Dimensional (2D: Stacked & Side by Side) & Three Dimensional (3D) test methods are evaluated. When comparing the investigated test extension strategies, it is found that test approach with stacked PCB levels alter the stress transferred to the component and can lead to a false reliability prediction. Depending upon the allowed mass load limit of the shaker system and stress levels involved, both 1D and 3D techniques can be used as complementary to one another. Outcomes of this study can further be used to provide guidance for future board level vibration test method.@en

The ongoing trend to deploy ICs in more complex and harsher applications, entails precise evaluation of solder joint reliability of components subjected to vibration loads. For this, a good understanding of the PCB vibrational motion during a board level vibration test is essential. This can only be achieved by a well characterized vibration test setup. The vibration motion can be recorded by using a contactbased measurement approach, i.e. using an accelerometer, or a contactless measurement configuration, i.e. using a Laser Doppler Vibrometer (LDV). This paper evaluates both measurement techniques by recording the PCB dynamic response, i.e. the resonance frequency and peak-to-peak displacement, in a board level vibration test set up. Bare and assembled printed circuit boards (PCBs) are investigated using different PCB form factors and package outlines (Wafer Level Chip Scale Package (WLCSP) and Ball Grid Array (BGA)), showing that LDV enables better lateral resolution and a more accurate measurement solution. Especially when the weight of the accelerometer cannot be neglected compared to the weight of the component on the PCB. An accelerometer is shown to perturb the PCB vibration motion. It is found that depending upon the test objectives and PCB electronic system involved, both techniques can be used as complementary to one another. The accelerometer weight may give rise to substantial modification of vibration response which can be used to simulate the presence of a component on a bare PCB. In addition, both methods are expected to recognize the same trends when e.g. studying the environmental impact during vibration tests. Finally, the experimental observations are@en

Technologies are focusing on empoweringconsumers with more functionalities into compactassemblies such as ball-grid array (BGA) and Chip ScalePackaging (CSP), offering small form factors to enablehigh-density semiconductor applications. Reliableperformance under drop test conditions is of paramountimportance for components targeted for some hand-heldapplications.Drop testing per JESD22-B111, prescribed by the JointElectronic Device Engineering Council (JEDEC), is anindustrial standard to characterize mechanicalreliability of solder joints subject to drop impact underthe specified test conditions. This specification wasrecently revised to JESD22-B111A version, with intent toprovide homogenous stress distribution for allcomponents mounted on the newly prescribed PCBlayout.The objective of this paper is to assess the impact of thesetest board changes on drop test performance of solderinterconnects and failure modes generated. It is carriedout by recording the board dynamic response upon dropimpact for test boards with three different form factors.It is complemented well with the Finite ElementModelling (FEM) developed for the studied drop testsettings. The investigation is supported by targetedexperiments on some prominent package styles. Thedrop test results show increased characteristic lifetime ofsolder joints when dropped using the square shaped testboard defined by JESD22-B111A as compared to theoutstanding studied specifications. This observation islinked to the impact of changing drop impact pulse, PCBform factor and build-up construction on the boarddynamics such as resonance frequency modes and PCBdeformation.@en