Understanding the Impact of PCB Changes in the latest Published JEDEC Board Level Drop Test Method

Conference paper (2018)

Authors

V. Thukral NXP Semiconductors
Affiliation
External organisation
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Published Date

2018

Language

English

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Affiliation

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Abstract

Technologies are focusing on empoweringconsumers with more functionalities into compactassemblies such as ball-grid array (BGA) and Chip ScalePackaging (CSP), offering small form factors to enablehigh-density semiconductor applications. Reliableperformance under drop test conditions is of paramountimportance for components targeted for some hand-heldapplications.Drop testing per JESD22-B111, prescribed by the JointElectronic Device Engineering Council (JEDEC), is anindustrial standard to characterize mechanicalreliability of solder joints subject to drop impact underthe specified test conditions. This specification wasrecently revised to JESD22-B111A version, with intent toprovide homogenous stress distribution for allcomponents mounted on the newly prescribed PCBlayout.The objective of this paper is to assess the impact of thesetest board changes on drop test performance of solderinterconnects and failure modes generated. It is carriedout by recording the board dynamic response upon dropimpact for test boards with three different form factors.It is complemented well with the Finite ElementModelling (FEM) developed for the studied drop testsettings. The investigation is supported by targetedexperiments on some prominent package styles. Thedrop test results show increased characteristic lifetime ofsolder joints when dropped using the square shaped testboard defined by JESD22-B111A as compared to theoutstanding studied specifications. This observation islinked to the impact of changing drop impact pulse, PCBform factor and build-up construction on the boarddynamics such as resonance frequency modes and PCBdeformation.