As big strides were being made in many science fields in the 1970s and 80s, faster computation for solving problems in molecular biology, semiconductor technology, aeronautics, particle physics, etc., was at the forefront of research. Parallel and super-computers were introduced, which enabled problems of a higher level of complexity to be solved. At about the same time, Nobel-laureate physicist Richard Feynman launched what seemed at the time a wild idea; to build a computer based on quantum physics concepts such as superposition and entanglement [1]. The outrageousness of his ideas is documented in the book 'Surely, You're Joking, Mr. Feynman' [2].

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Device characteristics at cryogenic temperatures can deviate significantly from their room temperature behaviour. For example, the threshold voltage of a MOSFET can increase by more than 100 mV when it is cooled down to 4.2 K, as shown in this thesis. If a designer is not aware of this shift, circuits that work as intended at room temperature can potentially fail at deep-cryogenic temperatures due to the resulting change in bias points, or even due to devices that are unable to be switched on. Device characterization is an indispensable step in building models for circuit designers. Foundries characterize their technology over the standard military temperature range (-55 to 125 ◦C) and generally do not supply compact models (yet) that are valid at deep-cryogenic temperatures. Therefore, designers of cryogenic circuits have to rely on back-of-the-envelope calculations and must build in margins to allow for parameter shifts, as they are unable to fully simulate their designs with use of the existing electrical simulators. These margins cause circuits to most likely occupy more silicon area than required and thus operate at lower speeds and with increased power dissipation compared to an optimized circuit. As the power budget is severely limited, this is a very important challenge of (current) cryogenic circuit design. Worst of all, circuits deviating from the stringent specifications for quantum control can lead to lower fidelity of quantum operations. In order to overcome these challenges, cryogenic device characterization needs to be carried out, to investigate and capture the impact of low temperatures on different device parameters. A convenient temperature to operate cryogenic circuits at, is that of liquid helium, which lies around 4.2 K. Therefore, most characterizations are carried-out at this temperature. Effort was already devoted to characterization and modeling at these temperatures by other groups, however, not much attention was spent on the impact of these extreme temperatures on device matching and self-heating in advanced processes. The work presented in this thesis, therefore, focuses on the design and characterization of test chips in an advanced 40-nm process, and the subsequent modeling of device mismatch and self-heating at cryogenic temperatures.@en

This work presents an experimental study of different components (resistors, diodes, transistors) in a standard 40-nm bulk CMOS process for their suitability as integrated cryogenic temperature sensors down to a temperature of 4.2K. It was found that most devices can be employed as sensors down to temperatures of approximately 50K, below which non-ideal effects such as non-linear behaviour and decreased sensitivity start to dominate. The Dynamic-Threshold MOS (DTMOS) was found to be a very promising candidate for its linearity, low forward-voltage-drop and sensitivity down to 8K. Moreover, as previous research indicated that cryogenic self-heating raises the local chip temperature to tens of Kelvins already at moderate power levels, the aforementioned sensing limitations at very low temperatures are expected to be of less importance in realistic applications. The results presented in this work contribute to the further integration of classical cryo-CMOS control electronics and qubits, towards a fully scalable quantum computer.

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This work presents a self-heating study of a 40-nm bulk-CMOS technology in the ambient temperature range from 300 K down to 4.2 K. A custom test chip was designed and fabricated for measuring both the temperature rise in the MOSFET channel and in the surrounding silicon substrate, using the gate resistance and silicon diodes as sensors, respectively. Since self-heating depends on factors such as device geometry and power density, the test structure characterized in this work was specifically designed to resemble actual devices used in cryogenic qubit control ICs. Severe self-heating was observed at deep-cryogenic ambient temperatures, resulting in a channel temperature rise exceeding 50 K and having an impact detectable at a distance of up to 30 μm from the device. By extracting the thermal resistance from measured data at different temperatures, it was shown that a simple model is able to accurately predict channel temperatures over the full ambient temperature range from deep-cryogenic to room temperature. The results and modeling presented in this work contribute towards the full self-heating-aware IC design-flow required for the reliable design and operation of cryo-CMOS circuits.

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Quantum-based systems, such as quantum computers and quantum sensors, typically require a cryogenic electrical interface, which can be conveniently implemented using CMOS integrated circuits operating at cryogenic temperatures (cryo-CMOS). Reliable simulation models are required to design complex circuits, but CMOS transistor electrical characteristics at cryogenic temperatures substantially deviate from the behavior at room temperature, and no standard physics-based model exists for cryo-CMOS devices. To circumvent those limitations, this paper proposes the use of Artificial Neural Networks (ANN) and an associated training (extraction) procedure that automatically generates cryo-CMOS device models directly from experimental data. A device model for the DC characteristics of 40-nm CMOS transistors over a wide range of bias conditions, device geometries and temperatures from 4 K to 300 K has been generated and used to simulate voltage-reference circuits over a wide temperature range (4 K - 300 K). The potential application to dynamic/high-frequency circuits is demonstrated by enhancing the basic model with ANN-based nonlinear multi-terminal capacitive elements to simulate a ring oscillator. Preliminary results showing a good match between simulations and experiments demonstrate the feasibility and practicality of the proposed approach.

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This paper presents a device matching study of a commercial 40-nm bulk CMOS technology operated at cryogenic temperatures. Transistor pairs and linear arrays, optimized for device matching, were characterized over the temperature range from 300 K down to 4.2 K. The device parameters relevant for mismatch, i.e., the threshold voltage and the current factor, were extracted, from which the change in both absolute value and variability as a function of temperature and device size were investigated. It is shown that the Pelgrom scaling law is valid also at 4.2 K and that the simplified Croon model is able to accurately predict drain-current mismatch from moderate to strong inversion over the entire temperature range. Additionally, the characterization of linear device arrays shows exacerbated edge-effects at extremely low temperatures, thus requiring the addition of dummy devices at the array boundary. The result of this study is the first model capable of predicting mismatch over a wide range of operating regions and temperatures.

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Accurate and low-noise generation and amplification of microwave signals are required for the manipulation and readout of quantum bits (qubits). A fault-tolerant quantum computer operates at deep cryogenic temperatures (i.e., <100 mK) and requires thousands of qubits for running practical quantum algorithms. Consequently, CMOS radio-frequency (RF) integrated circuits operating at cryogenic temperatures down to 4 K (Cryo-CMOS) offer a higher level of system integration and scalability for future quantum computers. In this paper, we extensively discuss the role, benefits, and constraints of Cryo-CMOS for qubits control and readout. The main characteristics of the CMOS transistors and their impacts on RF circuit designs are described. Furthermore, opportunities and challenges of low noise RF signal generation and amplification are investigated.

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The design of cryogenic interface electronics enabling future scalable quantum computers requires the accurate characterization and modeling of nanometer CMOS processes at cryogenic temperatures. To this end, this paper presents the mismatch characterization of 40-nm bulk CMOS transistors over the temperature range from 300 K down to 4.2 K. Measured data confirm that variability increases at cryogenic temperatures, and analysis of such data proves the validity of both the Pelgrom and the Croon models, which describe the mismatch dependency on device area and bias conditions, respectively.

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