In the pursuit of ever larger bandwidths, in recent years GHz-rate continuous-time (CT) oversampled ADCs have been reported in literature that achieve bandwidths of hundreds of MHz and have even exceeded the GHz barrier [1]-[3]. As impressive as these bandwidths are for CT ADCs, the required ADC architectures are complex, are sensitive to layout parasitics due to the high sampling rates, and most important of all, are power hungry, consuming several hundreds of mW. In this paper, we propose a filtering rnulti-stage noise-shaping (MASH) ΔΣ ADC architecture that overcomes the abovementioned drawbacks. Passive delay compensating filters [4] are used to realize broadband and deep suppression of the input signal component at the internal filter nodes of the ADC. As a result, no interstage DACs are needed, which are commonly required to generate the quantization error replicas in a MASH ΔΣ ADC, saving substantial power and greatly reducing the parasitic load of the high-speed critical nodes. Moreover, because of the absence of signal content at the internal filter nodes, the backend stages of the MASH architecture have relaxed linearity requirements and can be implemented with simple low-power Gm-C filters. Precise excess loop delay and excess phase compensation are accomplished with a partly resistive and capacitive stabilization DAC, enabling very-high-speed operation of the ΔΣ loops. The realized MASH ADC is sampled at 5GHz and achieves 68dB/65dB DR/peak SNDR over a 360MHz bandwidth, -78dBc THD at -1dBFS for a 115MHz input signal, and consumes 158mW. Implemented in a mature 40nm CMOS technology, the ADC occupies only 0.21 mm2 core area, achieves 2× lower power, 5dB higher Schreier FOM and 2× lower Walden FOM compared to state-of-the-art broadband CT ADCs in advanced 16nm-28nm nodes [1]-[3].

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This paper analyzes the error mechanisms that limit the dynamic range (DR) of wide-bandwidth, low-OSR continuous-time (CT) multi-stage noise-shaping (MASH) ΔΣM and proposes a tool, the Signal Leakage Function (SLF), to optimize the architecture, and hence improving DR. The SLF provides new insights on finding the key parameters which influence the inter-stage signal leakage and thus the inter-stage gain (IG). These insights would lead not only to increasing the overall dynamic range in a very power-efficient way, but also decreasing the performance sensitivity to mismatches and other variations.@en

This paper proposes an architecture design approach for a wideband continuous-time (CT) ΣΔ modulator with ultra-low oversampling ratio (OSR). The ultra-low OSR is beneficial in terms of power consumption for both the clock distribution network and the subsequent decimation filter. In this work, three signal feedforward paths and an additional feedback path are used to reduce the power consumption. Extensive system-level simulations demonstrate the effectiveness of the proposed solutions. Furthermore, this work verifies the proposed methods by transistor-level design and simulations of a 2 GHz 4^th-order CT ΣΔ modulator achieving an SNDR of 46 dB in a signal band of 250 MHz while consuming only 1.91 mW of power in 40 nm CMOS. The proposed solutions enable CT ΣΔ modulators for low power ultra-wideband (UWB) applications.

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This paper presents a 2 GHz 4-bit asynchronous successive approximation register (SAR) quantizer to enable an ultra-wideband continuous-time (CT) sigma-delta modulator (SDM). Low latency is required for the stability of the SDM. The excess-loop-delay compensation (ELDC) is embedded in the SAR quantizer by adding an extra switched-capacitor DAC segment with two separate reference voltages. To achieve high speed, a g_m-boosted StrongARM latch and the monotonic switching scheme are used. This paper presents the transistor-level circuit implementation and the complete verification of the CT SDM. Simulation results show the power consumption of this SAR-based quantizer including ELDC is 0.98 mW, leading to a very competitive Figure-of-Merit of 30.6 fJ/conv.-step.

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