This paper presents a SAR-assisted Continuous-time Delta-Sigma (CT Δ Σ ) ADC, which combines the energy efficiency of SAR ADCs with the relaxed driving requirements of CT Δ Σ ADCs, as well as similar anti-alias filtering. When clocked at 2.4GHz, the ADC achieves 77.5dB SNDR in 40MHz BW. It consumes 3.2mW, resulting in a state-of-the-art Walden FoM of 6.5fJ/cs and a Schreier FOM of 178.5dB.

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This paper presents a 2 GHz 4-bit asynchronous successive approximation register (SAR) quantizer to enable an ultra-wideband continuous-time (CT) sigma-delta modulator (SDM). Low latency is required for the stability of the SDM. The excess-loop-delay compensation (ELDC) is embedded in the SAR quantizer by adding an extra switched-capacitor DAC segment with two separate reference voltages. To achieve high speed, a g_m-boosted StrongARM latch and the monotonic switching scheme are used. This paper presents the transistor-level circuit implementation and the complete verification of the CT SDM. Simulation results show the power consumption of this SAR-based quantizer including ELDC is 0.98 mW, leading to a very competitive Figure-of-Merit of 30.6 fJ/conv.-step.

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This paper presents a 2 GS/s 5-b single-channel SAR ADC in 28 nm CMOS. The ADC uses a gm-boosted StrongARM comparator to achieve the highest reported sampling frequency for a non-time-interleaved SAR ADC. Its high sampling frequency, large input signal capability and one clock cycle latency make the ADC suitable for time-interleaved, multi-stage and feedback ADC architectures. The ADC occupies 900 μm2 and consumes 1.25 mW from a 0.9 V supply. Without calibration, and when operated at 1.5 GS/s it achieves 30.3 dB SNDR (FOMw=31.2 fJ/conv.-step). This drops slightly, to 27.4dB, at the maximum sampling rate of 2 GS/s.
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