A 3.2mW SAR-assisted CTΔΣ ADC with 77.5dB SNDR and 40MHz BW in 28nm CMOS

Conference paper (2019)

Authors

P. Cenci Electronic Instrumentation - EEMCS
M. Bolatkale Electronic Instrumentation - EEMCS , NXP Semiconductors
Robert Rutten NXP Semiconductors
M. Ganzerli NXP Semiconductors
K.A.A. Makinwa Microelectronics
Lucien Breems NXP Semiconductors
Research Group
Electronic Instrumentation (EEMCS) (TU Delft)
Copyright: © 2019 P. Cenci, M. Bolatkale, R. Rutten, M. Ganzerli, G. Lassche, K.A.A. Makinwa, Lucien Breems
DOI: https://doi.org/10.23919/VLSIC.2019.8778176
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Published Date

2019

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Research Group

Electronic Instrumentation

Abstract

This paper presents a SAR-assisted Continuous-time Delta-Sigma (CT Δ Σ ) ADC, which combines the energy efficiency of SAR ADCs with the relaxed driving requirements of CT Δ Σ ADCs, as well as similar anti-alias filtering. When clocked at 2.4GHz, the ADC achieves 77.5dB SNDR in 40MHz BW. It consumes 3.2mW, resulting in a state-of-the-art Walden FoM of 6.5fJ/cs and a Schreier FOM of 178.5dB.

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