The increased use of mobile appliances such as mobile phones and navigation systems in today's society has resulted in an increase in reliability issues related to drop performance. Mobile appliances are dropped several times during their lifespan and the product is required to survive common drop accidents. A widely accepted method to assess the drop reliability of microelectronics on board-level is the drop impact test. this test had been standardized by international councils such as Joint Electron Device Engineering Council and is widely adopted throughout the industry. In this research the solder loading is investigated by combining high-speed camera measurements of several drop impact tests with verified finite element models. These simulation models are developed in order to gain an insight in the loading pattern of solder joints based on interconnect layout, drop conditions, and product specifications prior to physical prototyping. Deflections and frequencies during drop testing are measured using a high-speed camera setup. The high-speed camera experiments are performed on two levels: machine level (rebounds with and without a catcher) and product level (with different levels of energy and different pulse times). Parametric (dyanamic and quasistatic) 3D models are developed to predict the drop impact performance. The experimental results are used to verify and enhance the simulation models, e.g. by tuning the damping parameters. As a result, the verified models can be used to determine the location of the critical solder joint and to obtain estimates of the solder lifetime performance. Keywords: drop impact reliability, drop impact modeling, chip scale packages, high-speed camera experiment.@en

In this paper, strain gauges are used to measure the dynamic response during drop impact. A set of high-speed data acquisition system is used to capture the real-time response of critical locations. Finite Element Modelling is used to determine where to place the strain gauge measurements. Two board level drop impact test methods, A and B, are compared by the strain gauge measurements. Results show significant differences in strain amplitude, strain rate, frequency, rebound, and damping. Method B produces higher strain amplitude, stronger rebound, and less damping, while method A produces higher frequency and strain rate. Damping and rebound are important factors for both test methods. The differences of two test methods are due to the contributions from test condition and test board. Combination test were conducted to investigate the contribution of test condition and test board. Results show that test board dominates strain amplitude, frequency, mode and damping, while test condition shows influence on strain amplitude and rebound. Test condition A produces higher strain amplitude, while test condition B produces stronger rebound. Test board A produces higher frequency, while test board B produces higher strain amplitude and less damping. Test board contributes more to the strain amplitude than test condition. Strain rate is dependent on both the test condition and test board.@en

The increased use of mobile appliances in today's society has resulted in an increase of reliability issues related to drop performance. A common method to assess the drop performance is the JEDEC specified drop impact test [1]. In this research the solder loading is investigated by means of drop impact simulations and high-speed camera measurements. The measurements are used to enhance the simulations by tuning the damping parameters. This results in models that are replicating the drop impact amplitudes and are thereby capable of determining the critical solder joint.@en

The increased use of mobile applicances in today's society has resulted in an increase of reliability issues related to drop performance. Mobile appliances are dropped multiple times during their lifespan and the product is required to survive common drop accidents. The use of lead-free solder compositions and the decreasing size of microelectronics aggravated the sensitivity of these products towards drop failures. Also, the use of miniature IC packages like Wafer Level Chip Scale Packages (WLCSP) with smaller lead sizes resulted in a decreased amount of material available to absorb the loading caused by a drop. A widely accepted method to assess the drop reliability of microelectronics on board-level is the drop impact test. The drop impact test has been standardized by international councils like JEDEC and is widely adopted throughout the industry. The intention of the drop test is to assess the overall product reliability towards dropping, focusing on the solder interconnections. These solder interconnections are usually the first link in the chain to fail. Clearly the drop impact reliability of a product is also influenced by numerous design factors like material compositions, ball layout and product size as well as manufacturing conditions. Solder loading is investigated in this research by using high-speed camera recordings of several drop impact tests with verified Finite Element models. These simulation models are developed in order to gain an insight on the loading pattern of solder joints based on product specifications, interconnect layout and drop conditions prior to physical prototyping. Deflections and frequencies during drop testing are measured using a high-speed camera setup. The high-speed camera experiments are performed on two levels: product level (with different levels of energy and different pulse times) and machine level (rebounds with and without a catcher). Parametric (dynamic and quasi static) 3D models are developed to predict the drop impact performance. The experimental results are used to verify and enhance the simulation models, e.g. by tuning the damping parameters. As a result, the verified models can be used to determine the location of the critical solder joint and to obtain estimates of the solder lifetime performance.@en