This article presents a 4-to-5GHz LC oscillator operating at 4.2K for quantum computing applications. The phase noise (PN) specification of the oscillator is derived based on the control fidelity for a single-qubit operation. To reveal the substantial gap between the theoretical predictions and measurement results at cryogenic temperatures, a new PN expression for an oscillator is derived by considering the shot-noise effect. To reach the optimum performance of an LC oscillator, a common-mode (CM) resonance technique is implemented. Additionally, this work presents a digital calibration loop to adjust the CM frequency automatically at 4.2K, reducing the oscillator's PN and thus improving the control fidelity. The calibration technique reduces the flicker corner of the oscillator over a wide temperature range (10 $\times $ and 8 $\times $ reduction at 300K and 4.2K, respectively). At 4.2K, our 0.15-mm2 oscillator consumes a 5-mW power and achieves a PN of -153.8dBc/Hz at a 10MHz offset, corresponding to a 200-dB FOM. The calibration circuits consume only a 0.4-mW power and 0.01-mm2 area.

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In this article, we present a 4.5-5.1-GHz fractional-N digitally intensive phase-locked loop (DPLL) capable of maintaining its performance in face of a large supply ripple, thus enabling a direct connection to a switched-mode dc-dc converter. Supply pushing of its inductor-capacitor (LC) oscillator is suppressed by properly replicating the supply ripple onto the gate of its tail current transistor, while the optimum replication gain is determined by a new on- chip calibration loop tolerant of supply variations. A proposed configuration of cascading a supply-insensitive slope generator with an output of a current digital-to-analog converter (DAC) linearly converts the phase error timing into a corresponding voltage, which is then quantized by a successive approximation register (SAR) analog-to-digital converter (ADC) to generate a digital phase error. We also introduce a low-power ripple pattern estimation and cancellation algorithm to remove the phase error component due to the supply-induced delay variations of loop components. Implemented in 40-nm CMOS, the DPLL prototype achieves the performance of 428-fs rms jitter, <-55-dBc fractional spur, and <-54-dBc maximum spur while consuming 3.25 mW and being subjugated to a sinusoidal or sawtooth supply ripple of 50 mVpp at 50-MHz reference divided by 3, 6, or 12.

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The scaling of CMOS technology in deep submicron process nodes is accompanied by the integration of more and more functional blocks of a system, whether digital or analog/RF, onto the same chip (i.e., system-onchip, SoC). These blocks would also place different requirements on their power supplies. To provide various static or dynamically controlled supply voltages needed by the SoC, a dedicated power management unit (PMU) is typically deployed. Following the same trend of system integration, implementing the PMU on-die is also highly desired. The core of a PMU consists of several sets of voltage regulators that convert the output level of the energy source to the multiple supply voltages required by the integrated system. The DC-DC converters (switching regulators) and the low-dropout (LDO) linear regulators are normally employed in cascade for high power efficiency and for suppressing ripple amplitude demanded by the supply sensitive blocks, respectively. Although much effort has been devoted to the research on the design of fully integrated, or the so-called ‘capacitor-less’ LDOs, little has been done for the co-analysis and co-design of these LDOs with the load circuitry they power. Frequency synthesizers have found wide applications in various systems. The phase-locked loop, as one of the most commonly used frequency synthesis techniques, modulates the oscillator in a feedback manner to generate the desired loop output. The first part of this thesis (Chapters 2 and 3) focuses on the power efficiency of the capacitor-less LDO when powering a PLL. Since the PLL, especially its oscillator, is sensitive to the supply perturbations, the LDO should provide a high power supply rejection (PSR) at the ripple frequency, which could be in the range of 153 154 Summary several to tens of megahertz for integrated DC-DC converters, with a low output noise. The dropout voltage of the LDO is then determined by the required PSR, consuming extra voltage headroom and degrading the efficiency of the system. The tolerable output noise generally limits the minimum quiescent current consumed by the error amplifier (EA) and the feedback resistors in the LDO. Owning to the stringent requirement of the supply noise imposed by the oscillator in order to preserve its inherent phase noise performance, the efficiency of the corresponding LDO would be further degraded by a large factor due to its quiescent current consumption. Based on the analysis above, it deems beneficial to power the PLL directly from the output of DC-DC converters. Taking this step further, different scenarios of powering the SoC are also identified and briefly discussed at the end of the first part. To enable the proposed direct connection, the modules in the PLL should be able to tolerate the output ripples from such converters. In the second part of this thesis (Chapters 4 and 5), a fractional-N digitally intensive PLL (DPLL) architecture capable of maintaining its performance under a large (i.e., 50mVpp) supply ripple is developed. The digital implementation is selected due to its ability to incorporate various digital calibration techniques with relative ease. The supply pushing of the LC oscillator used in the DPLL is suppressed by the proposed feed-forward ripple replication and cancellation technique, which replicate the supply ripple to the gate of its tail current source with a proper gain, stabilizing the oscillator tail current, and correspondingly, the oscillation swing. The optimal gain is calibrated on-chip through amplifying the oscillation amplitude variation and locating the control setting corresponding to the minimum value. The time error between the reference and the divided output of the oscillator is linearly converted into voltage domain through the current-mode supply insensitive slope generator, with its input range being halved by resampling the output of the multi-modulus divider (MMDIV), driven by second-order .. modulation, with both edges of the oscillation signal. The output of a current DAC operating in parallel is also cascaded with the slope generator during phase detection to limit the dynamic range of the SAR ADC used to digitize the phase error. A low-power ripple pattern estimation and cancellation algorithm is also inserted at the ADC output to remove 155 the effect of the output delay perturbations of loop components under the supply ripple. Employing all these techniques, the proposed DPLL demonstrates, for the first time ever, the acceptable performance while operating under a large 50mVpp supply ripple. @en

In this paper, we propose a method to suppress supply pushing of an LC oscillator such that it may directly operate from a switched-mode dc-dc converter generating fairly large ripples. A ripple replication block (RRB) generates an amplified ripple replica at the gate terminal of the tail current source to stabilize the oscillator's tail current and thus its oscillating amplitude. The parasitic capacitance of the active devices and correspondingly the oscillation frequency are stabilized in turn. A calibration loop is also integrated on-chip to automatically set the optimum replication gain that minimizes the variation of the oscillation amplitude. A 4.9-5.6-GHz oscillator is realized in 40-nm CMOS and occupies 0.23 mm&#x00B2; while consuming 0.8-1.3 mW across the tuning range (TR). The supply pushing is improved to &lt;1 MHz/V resulting in a low &lt;-49-dBc spur due to 0.5-12-MHz sinusoidal supply ripples as large as 50 mVpp. We experimentally verify the effectiveness of the proposed technique also in face of saw-tooth, multi-tone, and modulated supply ripples.

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To characterize an on-chip programmable delay in a low-cost and high-resolution manner, a built-in self-test based on a first-order ?? time-to-digital converter with self-calibration is proposed and implemented in TSMC 28-nm CMOS. The system is self-contained, and only one digital clock is needed for the measurements. A system self-calibration algorithm is proposed to calibrate nonlinearities of the analog circuitry. The operation is robust over PVT variations since the delay information is normalized to the input clock period. To verify the proposed idea, two different digital-to-time converters performing the on-chip delay are measured and analyzed at 50-MHz clocking frequency with 0.65-ps standard time deviation per measurement.@en

We propose a ring-based quadrature LC-tank oscillator for Internet-of-Things (IoT) that can operate under a 350-mV supply voltage of energy harvesters. The oscillator is based on a series LC tank, with additional control circuitry to realize a nearly instantaneous start-up of one/two RF cycles to facilitate a deeply duty-cycled burst-mode operation of IoT. Fabricated in TSMC 28nm CMOS, the prototype consumes less than 1.3mW from 350mV supply and 0.07mm2 in area, while achieving phase noise of better than −118dBc/Hz @3MHz. Frequency tuning range is 2.24∼2.61GHz@en

This paper proposes a digital-to-time converter (DTC)-assisted fractional-N wide-bandwidth all-digital phase-locked loop (ADPLL) with a fine-resolution time-to-digital converter (TDC). The TDC employs a two-channel time-interleaved time-domain register with an implicit adder/subtractor realizing an error-feedback topology. Such an error-feedback unit of a first-order Δ Σ -TDC can be cascaded as a multi-stage noise shaping configuration to achieve higher-order noise-shaping and, thereby, low in-band phase noise (PN) of the ADPLL. A digitally controlled oscillator with a transformer and a pair of cross-coupled NMOS amplifiers exploits magnetic and capacitive coupling to achieve nearly an octave frequency coverage, i.e., 1.73-3.38 GHz (after a ÷2 division). Fabricated in 40-nm CMOS, the ADPLL achieves better than -110-dBc/Hz in-band PN and occupies an active area of 0.5 mm². With a 50-MHz reference clock, a 2-GHz output RF clock, and a loop bandwidth of 800 kHz, this prototype achieves 420-fsrms jitter, integrated from 1-kHz to 30-MHz offset, while drawing 10.7 mW.

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We present a digital-to-time converter (DTC)-assisted fractional-N wide-bandwidth all-digital PLL (ADPLL). It employs a MASH ΔΣ time-to-digital converter (TDC) to achieve low in-band phase noise, and a wide-tuning range digitally-controlled oscillator (DCO). Fabricated in 40nm CMOS, the ADPLL consumes 10.7 mW while outputting 1.73 to 3.38 GHz (after a ÷2 division) and achieves better than -109 dBc/Hz in-band phase noise and 420fsrms integrated jitter.@en