This paper presents a wakeup timer in 40-nm CMOS for Internet-of-Things (IoT) applications based on a bang-bang Digital-intensive Frequency-Locked Loop (DFLL). A self-biased Σ Δ Digitally Controlled Oscillator (DCO) is locked to an RC time constant via a feedback loop consisting of a single-bit chopped comparator and a digital loop filter, thus maximizing the use of digital circuits while keeping only the RC network and the comparator as the sole analog blocks. Analysis and behavior level simulations of the DFLL have been carried out to guide the optimization of the long-term stability and frequency accuracy of the timer. High frequency accuracy and a 10× enhancement of long-term stability is achieved by the adoption of chopping to reduce the effect of comparator offset and 1/f noise and by the use of Σ Δ modulation to improve the DCO resolution. Such highly digitized architecture fully exploits the advantages of advanced CMOS processes, thus enabling operation down to 0.7 V and a small area (0.07 mm2). The proposed timer achieves the excellent energy efficiency (0.57 pJ/cycle at 417 kHz at 0.8-V supply) over prior art while keeping excellent on-par long-term stability (Allan deviation floor < 20 ppm) and temperature stability (33 ppm°Cat 0.8-V supply).

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For remote vital signs and occupancy detection in many smart home/building applications, radar sensors are a preferred option over cameras, due to privacy preservation and robustness to ambient light conditions. These radars not only need to provide precise range and vital signs information over meters distance, but also preferably can operate on a battery up to a few months or even years, for cost and practical reasons (like smoke detectors). State-of-the-art remote vital-sign sensors typically use an impulse-radio UWB (IR-UWB) radar [1,2] because it provides a range resolution <20 cm. However, their power consumption is typically in the order of 100's of mW, preventing long-term maintenance-free battery-powered operations. Although mains power can be used to supply such radars, this is not always available, depending on the location and the building type, and the installation cost (e.g., power routing) is significantly higher than for battery-powered ones. In this work, a burst-chirp radar with an energy-efficient chirp generation is proposed, leading to a record-low power consumption of 680 μW.

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In this paper, we propose a method to suppress supply pushing of an LC oscillator such that it may directly operate from a switched-mode dc-dc converter generating fairly large ripples. A ripple replication block (RRB) generates an amplified ripple replica at the gate terminal of the tail current source to stabilize the oscillator's tail current and thus its oscillating amplitude. The parasitic capacitance of the active devices and correspondingly the oscillation frequency are stabilized in turn. A calibration loop is also integrated on-chip to automatically set the optimum replication gain that minimizes the variation of the oscillation amplitude. A 4.9-5.6-GHz oscillator is realized in 40-nm CMOS and occupies 0.23 mm&#x00B2; while consuming 0.8-1.3 mW across the tuning range (TR). The supply pushing is improved to &lt;1 MHz/V resulting in a low &lt;-49-dBc spur due to 0.5-12-MHz sinusoidal supply ripples as large as 50 mVpp. We experimentally verify the effectiveness of the proposed technique also in face of saw-tooth, multi-tone, and modulated supply ripples.

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A 40-nm CMOS wakeup timer employing a bang-bang digital-intensive frequency-locked loop for Internet-of-Things applications is presented. A self-biased ΣΔ digitally controlled oscillator (DCO) is locked to an RC time constant via a single-bit chopped comparator and a digital loop filter. Such highly digitized architecture fully exploits the advantages of advanced CMOS processes, thus enabling operation down to 0.7 V and a small area (0.07 mm 2 ). Most circuitry operates at 32× lower frequency than the DCO in order to reduce the total power consumption down to 181 nW. High frequency accuracy and a 10× enhancement of long-term stability is achieved by the adoption of chopping to reduce the effect of comparator offset and 1/f noise and by the use of ΣΔ modulation to improve the DCO resolution. The proposed timer achieves the best energy efficiency (0.43 pJ/cycle at 417 kHz) over prior art while keeping excellent on-par long-term stability (Allan deviation floor <;20 ppm) and temperature stability (106 ppm/°C).@en

This paper presents a 1.8-2.7 GHz low-power ring-oscillator-based fractional-N injection-locked digital PLL (IL-DPLL) in 40-nm CMOS for Internet-of-Things clock generation. A two-path injection technique is proposed to improve the in-band phase noise and the integrated jitter of the implemented PLL by 6 dB and 1.8×, respectively. Furthermore, a digital foreground calibration is introduced to effectively reduce reference spurs in a short calibration time of 2 μs. In the worst-case channel, the proposed DPLL using a 64 MHz reference input shows a 1.6 ps integrated jitter, -43.6 dBc reference spur, -45.8 dBc fractional spur and 1 kHz frequency resolution while consuming 1.33 mW power.

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We propose an ultra-low-power (ULP) and low-voltage phase-tracking RX for IoT applications. Several popular standards are defined for IoT, e.g., IEEE802.15.4 and Bluetooth Low Energy (BLE), where they envision massive numbers of interconnected sensors; however, the cost of replacing/recharging batteries can become an impediment to their massive deployment. In this work, aggressively improving the transceiver energy efficiency, lowering the supply, and simultaneously reducing the cost (die area) of the design are our primary goals. Hence, we propose a digitally-controlled oscillator (DCO)-based phase-tracking RX, which efficiently combines frequency downconversion, channel selection, carrier generation and signal demodulation, all of which lead to an ultra-low-power, low-voltage and low-cost RX.

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