A 3.5–6.8 GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise

Wu, Y.; Shahmohammadi, M.; Chen, Y.; Lu, Ping; Staszewski, Bogdan

A 3.5–6.8 GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise

Conference paper (2016)

Authors

Y. Wu Electronics -

M. Shahmohammadi Electronic Components, Technology and Materials -

Y. Chen Electronics -

Ping Lu Lund University

Bogdan Staszewski University College Dublin, Electronics -

Research Group

Electronics () (TU Delft)

DTC Delta-sigma modulation Noise shaping Oscillators Phase noise TDC Tuning ADPLL Jitter Jitter Wide-bandwidth Delays DCO Phase noise BBPD Phase locked loops Digital phase locked loops Size 40 nm Frequency measurement MASH Digital-to-time converter Integrated circuit noise Time-digital conversion DTC-assisted fractional-N all-digital PLL MASH ?S TDC Frequency 1.73 GHz to 3.38 GHz Frequency 3.5 GHz to 6.8 GHz Integrated jitter Low-in-band phase noise Power 10.7 mW Wide-tuning range DCO Wide-tuning range digitally-controlled oscillator Multi-stage noise shaping All digital PLL Wide-tuning range

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Published Date

2016

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Research Group

Electronics

Abstract

We present a digital-to-time converter (DTC)-assisted fractional-N wide-bandwidth all-digital PLL (ADPLL). It employs a MASH ΔΣ time-to-digital converter (TDC) to achieve low in-band phase noise, and a wide-tuning range digitally-controlled oscillator (DCO). Fabricated in 40nm CMOS, the ADPLL consumes 10.7 mW while outputting 1.73 to 3.38 GHz (after a ÷2 division) and achieves better than -109 dBc/Hz in-band phase noise and 420fsrms integrated jitter.