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Modeling of strained CMOS on disposable SiGe dots

Shape impacts on electrical/thermal characteristics

Journal article (2008) - S Fregonese, Y Zhuang, JN Burghartz

We proposed a new non-planar disposable SiGe dot (d-Dot) MOSFET based on Si-on-nothing technology. The new device concepts’ relies on self-assembled single-crystalline d-Dot. The d-Dot MOSFET is prone to a particularly high strain/stress from the underlaying SiGe 3D islands. We s ...

A Hicum SOI extension

Conference paper (2007) - S Fregonese, G Avenier, C Maneux, A Chantre, T Zimmer

Modeling of strained CMOS on disposable SiGe dots: Strain impacts on devices electrical characteristics

Journal article (2007) - S Fregonese, Y Zhuang, JN Burghartz

3D Simulation Study of Strained CMOS based on a disposable SiGe Dot Technology

Conference paper (2007) - S Fregonese, Y Zhuang, Joachim Burghartz

CNTFET Modeling and Reconfigurable Logic Circuit Design

Journal article (2007) - Ian O'Connor, JS Liu, T Dang, R Leveugle, F Gaffiot, F Prégaldiny, C Lallement, C Maneux, J Goguet, S Fregonese, T Zimmer, L. Anghel

A compact model for HBT on thin film SOI

Journal article (2006) - S Fregonese, G Avenier, C Maneux, A Chantre, T Zimmer

Thin ¿lm SOI HBT: A study of the effect of substrate bias on the electrical characteristics

Journal article (2006) - S Fregonese, G Avenier, C Maneux, A Chantre, T Zimmer

A computationally efficient physics-based compact bipolar transistor model for circuit design - Part II: Experimental results

Journal article (2006) - S Fregonese, S. Lehmann, T Zimmer, M. Schroter, D Céli, B Ardouin, H Beckrich, P Brenner, W Kraus

JFET test structures for monitoring strain-enhanced mobility

Conference paper (2006) - L. Shi, G. Lorito, V. Jovanovic, S Fregonese, L.K. Nanver

Prospects for complementary SiGeC BiCMOS on thin-film SOI

Conference paper (2006) - A Chantre, G Avenier, S Fregonese, F Judong, R Pantel, A Perrotin, B Rauber, L Rubaldo, F Saguin, T Schwartzmann, B Vandelle, T Zimmer, L Boissonnet, G Borot, P Bouillon, F Brossard, P Chevalier, F Deléglise, D Dutartre, J Duvernay

A computationally efficient physics-based compact bipolar transistor model for circuit design - Part I: model formulation

Journal article (2006) - M. Schroter, S. Lehmann, S Fregonese, T Zimmer

Analysis of CNTFET physical compact model

Conference paper (2006) - C Maneux, J Goguet, S Fregonese, T Zimmer, HC d'Honincthun, S Galdin-Retailleau

A transit time model for thin SOI Si/SiGe HBT

Conference paper (2005) - S Fregonese, G Avenier, C Maneux, A Chantre, T Zimmer

A self-aligned vertical HBT for thin SOI SiGeC BiCMOS

Conference paper (2005) - G Avenier, T Schwartzmann, C Maneux, T Zimmer, A Chantre, P Chevalier, B Vandelle, L Rubaldo, D Dutartre, L Boissonnet, F Saguin, R Pantel, S Fregonese

Network Analysis for SiGe HBT¿s thermal impedance modelling

Book chapter (2005) - H Mnif, JL Battaglia, PY Sulima, S Fregonese, T Zimmer

A transient measurement setup for electro-thermal characterisation for SiGe HBTs

Conference paper (2005) - PY Sulima, T Zimmer, H Beckrich, JL Battaglia, S Fregonese, D Céli

Investigation of fully- and partially-depleted self-aligned SiGeC HBTs on thin film SOI

Conference paper (2005) - G Avenier, P Chevalier, B Vandelle, D Lenoble, F Saguin, S Fregonese, T Zimmer, A Chantre

Study of a 3D thermal characterization of SiGe HBTS

Conference paper (2005) - PY Sulima, JL Battaglia, T Zimmer, S Fregonese, D Céli

Base-collector junction charge investigation of Si/SiGe HBT on thin film SOI