In this paper, we investigate an impact of voltage supply scaling on power consumption and performance of a new class of wireless receivers (RX) for Internet-of-Things (IoT) applications: a discrete-time (DT) superheterodyne architecture realized in nanoscale CMOS using inverter-based gm and switched capacitors. The power supply is partitioned into three separate domains: RF, intermediate frequency (IF) processing, and clocking, which allows them to be independently regulated to assess their respective impact. The DT-RX maintains its functionality, albeit with some acceptable loss of performance, when the core supplies are varied by as much as an octave, i.e., from the nominal 1.1 V down to 0.55V. The DT-RX IC is then connected to a switched-capacitor based voltage doubler array on a companion IC die such that the DT-RX can be powered at the octave range of 0.275-0.55 V from an energy harvester. The sensitivity at the doubler's 0.275/0.55 V input is -85/-95 dBm while consuming 1.0/2.4mW. Both ICs are implemented in TSMC 28-nm LP CMOS.

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We present an ultra-low-power Bluetooth Low Energy (BLE) transceiver for Internet of things (IoT) optimized for 28-nm CMOS. A transmitter (TX) employs an all-digital phase-locked loop (ADPLL) with switched current source digitally controlled oscillator (DCO) and class-E/F2 power amplifier. The proposed oscillator combines the benefits of low-supply voltage operation of conventional NMOS cross-coupled oscillators with high current efficiency of the complementary push-pull oscillators. It also reduces 1/f noise and supply pushing, thus allowing the ADPLL, after settling, to reduce its sampling rate or shut it off entirely during a direct DCO modulation. The switching power amplifier operates in class-E/F2 to maximally enhance its efficiency at low output power. The receiver (RX) operates in discrete time (DT) at high sampling rate ( ∼ 10 GSample/sec) with an intermediate frequency (IF) placed beyond 1/f noise corner of MOS devices. Multistage multi-rate charge-sharing (CS) band-pass filters (BPF) are placed to achieve high out-of-band linearity, low noise, and low power consumption. Furthermore, an integrated on-chip matching network serves both PA and LNTA, thus allowing a one-pin direct antenna connection with no extra band selection filters. The transceiver consumes 2.75 mW in RX and 3.7 mW in TX when delivering 0 dBm in BLE.@en

We present an ultra-low-power Bluetooth low-energy (BLE) transceiver (TRX) for the Internet of Things (IoT) optimized for digital 28-nm CMOS. A transmitter (TX) employs an all-digital phase-locked loop (ADPLL) with a switched current-source digitally controlled oscillator (DCO) featuring low frequency pushing, and class-E/F₂ digital power amplifier (PA), featuring high efficiency. Low 1/ f DCO noise allows the ADPLL to shut down after acquiring lock. The receiver operates in discrete time at high sampling rate (10 Gsamples/s) with intermediate frequency placed beyond 1/ f noise corner of MOS devices. New multistage multirate charge-sharing bandpass filters are adapted to achieve high out-of-band linearity, low noise, and low power consumption. An integrated on-chip matching network serves to both PA and low-noise transconductance amplifier, thus allowing a 1-pin direct antenna connection with no external band-selection filters. The TRX consumes 2.75 mW on the RX side and 3.7 mW on the TX side when delivering 0 dBm in BLE.

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This paper introduces a system-level approach to develop the first-ever fully discrete-time (DT) superheterodyne receiver (RX) for Internet-of-Things applications, such as Bluetooth low energy (BLE). It exploits fast switching speed and low internal capacitances of deep-nanoscale CMOS devices to realize a high intermediate-frequency (IF) architecture based on switched-capacitor-based charge-domain bandpass filtering. Power consumption is minimized by aggressively reducing the size of MOS devices and judiciously applying a sampling-rate decimation. The resultant increase in the flicker noise is mitigated by placing the IF frequency beyond the flicker corner frequency. Likewise, the decimation-induced aliasing is mitigated by DT filtering of preceding stages. The BLE RX is fully standard-compliant and achieves a record-low-power consumption of 2.75 mW (including its local oscillator) while delivering the state-of-the-art performance: 6.5-dB noise figure and -19-dBm third-order input intercept point, with a direct antenna connection and thus without the typical external bandpass filters.

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We present a new ultra-low-power (ULP) transceiver for Internet-of-Things (IoT) optimized for 28-nm CMOS. The receiver (RX) employs a high-rate (up to 10 GS/s) discrete-time (DT) architecture with intermediate frequency (IF) placed beyond the 1/f noise corner of MOS devices. New multistage multi-rate charge-sharing bandpass filters are adapted to achieve high out-of-band linearity, low noise and low power consumption. A transmitter (TX) employs an all-digital PLL (ADPLL) with switched-current-source digitally controlled oscillator (DCO) and switching PA. An integrated on-chip matching network serves both PA and LNTA, thus allowing a 1-pin direct antenna connection with no external antenna filters. The transceiver consumes 2.75mW in RX and 3.6mW in TX when delivering 0 dBm in Bluetooth LE.@en