Investigation on Transient Failure Mode of Asymmetric Trench Gate SiC MOSFET Under Single-Pulse Avalanche Stress

Conference paper (2023)

Authors

S. Wang Southern University of Science and Technology, Bio-Electronics - EEMCS
Yanlong Tan Research Institute of Fudan University, Ningbo
Chunjian Tan Southern University of Science and Technology
Xu Liu Southern University of Science and Technology
Shizhen Li Southern University of Science and Technology
Ke Liu Southern University of Science and Technology
Wucheng Yuan Southern University of Science and Technology
Tao Li PhasedCom Communication Technology Co.,Ltd
Kouchi Zhang Electronic Components, Technology and Materials - EEMCS
P.J. French Bio-Electronics - EEMCS
Huaiyu Ye Southern University of Science and Technology
Research Group
Bio-Electronics (EEMCS) (TU Delft)
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Published Date

2023

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Research Group

Bio-Electronics

Abstract

In this article, the avalanche withstand capability and transient failure model of commercial 1200 V asymmetric trench gate SiC MOSFETs are investigated by experiment and simulation under single-pulse unclamped inductive switching (UIS) conditions. The limiting avalanche current and limiting avalanche energy of the device are determined by evaluating the voltage and current waveforms, the power dissipation, and the avalanche energy curves before and during avalanche failure. Then, by using the calibrated simulation model, the sequence between the critical electric field stress and critical thermal stress suffered by the device is revealed, and the transient failure mode of the device is proved to be the thermal runaway. Moreover, after decapping the failed device, the failure mode of the device is further confirmed by analyzing the failure point. Finally, by using the focused ion beam (FIB) technology, the failure mechanism of the device is confirmed as a structural rupture caused by avalanche thermal stress.

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