In this article, the avalanche withstand capability and transient failure model of commercial 1200 V asymmetric trench gate SiC MOSFETs are investigated by experiment and simulation under single-pulse unclamped inductive switching (UIS) conditions. The limiting avalanche current and limiting avalanche energy of the device are determined by evaluating the voltage and current waveforms, the power dissipation, and the avalanche energy curves before and during avalanche failure. Then, by using the calibrated simulation model, the sequence between the critical electric field stress and critical thermal stress suffered by the device is revealed, and the transient failure mode of the device is proved to be the thermal runaway. Moreover, after decapping the failed device, the failure mode of the device is further confirmed by analyzing the failure point. Finally, by using the focused ion beam (FIB) technology, the failure mechanism of the device is confirmed as a structural rupture caused by avalanche thermal stress.@en

This paper proposes and simulates research on the reverse recovery characteristics of two novel superjunction (SJ) MOSFETs by adjusting the doping profile. In the manufacturing process of the SJ MOSFET using multilayer epitaxial deposition (MED), the position and concentration of each Boron bubble can be adjusted by designing different doping profiles to adjust the resistance of the upper half P-pillar. A higher P-pillar resistance can slow down the sweep out speed of hole carriers when the body diode is turned off, thus resulting in a smoother reverse recovery current and reducing the current recovery rate (d (Formula presented.) /d (Formula presented.)) from a peak to zero. The simulation results show that the reverse recovery peak current (I (Formula presented.)) of the two proposed devices decreased by 5% and 3%, respectively, compared to the conventional SJ. Additionally, the softness factor (S) increased by 64% and 55%, respectively. Furthermore, this study also demonstrates a trade-off relationship between static and reverse recovery characteristics with the adjustable doping profile, thus providing a guideline for actual application scenarios.

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In this paper, a novel bubble-shift super junction (SJ) MOSFET structure is proposed, and its main static electrical parameters and reverse recovery characteristics are simulated by TCAD software tool. By designing the P-pillar ion implantation windows with a certain offset, the bubble-shift SJ-MOSFET contains a curved pillar region in the upper half of the P-pillar. In the reverse recovery test of the proposed bubble-shift SJ-MOSFET, the peak reverse recovery current (I rrm ) is reduced from 16.04 A to 15.21 A, and the current drop rate (di/dt) is reduced from 1587 A/μs to 815 A/μs. Correspondingly, the proposed device achieves a better reverse recovery characteristic while sacrificing a small fraction of the drain-source breakdown voltage (BV) and drain-source special on-resistance (R on,sp ). Compared with the BV of 700 V and the R on,sp of 9 mΩ·cm 2 of the benchmark SJ-MOSFET. The proposed device has a BV of 650 V and a R on,sp of 12.4 mΩ·cm 2 . Mechanistically, the non-uniform depletion of the curved P-pillar reduces the carrier extraction rate, thereby prolonging the reverse current drop time (t f ) and increasing the softness factor (S) of the bubble-shift SJ-MOSFET.@en

The limitation of Silicon based power MOSFET was broken by the super-junction (SJ) structure, which can provide lower specific on-resistance and higher breakdown voltage compared with the conventional power MOSFET structure. Multi-epitaxial and multi-ion-implant technology, as a mature manufacturing process of the SJ structure, has been widely used in the field of SJ-MOSFET. Therefore, this process is applied to construct the cell structure of 650V SJ-MOSFET in our study. Based on practical application, high current caused by unexpected short circuit will induce an increasing of the internal temperature of SJ-MOSFET, which leads to an irreversible damage in the SJ-MOSFET devices. However, the short-circuit robustness of SJ-MOSFET is still unstable, and the structure needs to be further improved. In our study, the electrical performance of a 650V SJ-MOSFET with offset P-pillar is theoretically investigated by means of technology computer aided design (TCAD) when the SJ-MOSFET is short circuited. The results clearly show that the optimized SJ-MOSFET can withstand the source-drain voltage of 400V for at least 10 μs in the case of the short-circuit. The thermal distribution and peak temperature of the cell structure of SJ-MOSFET are also simulated to assist in the analysis of the short circuit capable of the device. In addition, the hole current density distribution of two SJ-MOSFETs is considered to gain insight into the effect of P-pillar parameters on the short-circuit robustness. The result represents that the structure with offset P-pillar can effectively improve the short-circuit capability.@en