The prosperity of the Internet-of-Things (IoT) imposes increasing demand on endpoint microcontroller-based devices' performance and energy efficiency. The MCUs are demanded to process the raw data acquired from the sensors with the integer-based workload, such as digital signal processing (DSP) algorithms and quantized neural network (QNN) inference. Snitch is a tiny RV32I control core based on RISC-V open-source instruction set architecture. Currently, the Snitch system built around the Snitch core aims to achieve high performance in floating-point applications. Novel hardware extensions have been implemented in its floating-point subsystem to achieve high floating-point unit (FPU) utilization, such as stream semantic registers (SSRs) and floating-point repetition (FREP) hardware loop. However, it only has RV32IM instruction set support for integer computation, which does not satisfy the increasing demand from the integer workload we mentioned. In this work, we present a unified Snitch architecture with integer extensions targeting integer workload acceleration. Some existing custom extensions to address performance bottlenecks in DSP and QNN applications were proposed, which are Xpulpimg ISA and sub-byte single-instruction-multiple-data (SIMD) ISA, respectively. Both extensions are built on the outdated version of Snitch in another many-core system Mempool. In our work, we first integrated the DSP-oriented ISA extension Xpulpimg and the sub-byte SIMD ISA extension into the mainline Snitch. Then we extended the existing floating-point SSR to have integer support. To evaluate the proposed extensions, we benchmarked the Snitch core complex (CC) with integer matrix multiplication algorithms and compared the performance between the baseline RV32IM and our extensions. A speedup of 5.9$\times$, 22.6$\times$, and 77.4$\times$ in terms of MACs/cycle with respect to the baseline was measured for 32-bit, 8-bit and 4-bit data sizes, respectively. Post-synthesis figures have been obtained from GlobalFoundries 22 nm technology for area and timing evaluations. Our integer extensions only introduced 12\% area overhead compared with the original FP-capable Snitch CC, and they led to no measurable impact in terms of the maximum effective frequency with FP extensions enabled.

Over the last decade, the recognition of the potential value of augmented reality (AR) and other human-machine interfaces has been growing. These applications are all based on depth sensing technologies. Among various depth sensing technologies, the Time-of-Flight (ToF) approach is emerging as a widely applicable method because it has the potential of reaching much longer distances at higher speed and accuracy, is natively suitable for mobile phones or AR.
One obvious problem is that the dToF system mainly targets the automotive industry or 3D imaging in close range, which means different power, accuracy, and fewer area requirements than mobile phone or AR applications. The application of the dToF system in the mobile phone or AR industry needs to be tested. The data volume is another problem of dToF. Usually, in the read out part, the dToF time-to digital converter (TDC)’s timestamps will all be saved into a histogram. The peak value of the histogram is the detected result. However, in a large pixels scenario, the area cost will be too much for mobile phone or AR applications if the whole histogram for all pixels is saved. Hence, an algorithm that can save histogram partially or find out the peak value without saving histogram is needed.
This thesis proposed two novel algorithms for the dToF system’s read out part and tested three other algorithms’ functions in mobile phone or AR applications. With the Lambertian model and probabilistic theory, a module of the dToF system is built using MATLAB to generate a testing dataset. Besides, introductions to depth-sensing technologies, single-photon avalanche diode (SPAD) sensors, and dToF systems will be given before the core chapters of the thesis.

Renewed interest in memory technologies such as memristors and ferroelectric devices can provide opportunities for traditional and non-traditional computing systems alike. To make versatile, reprogrammable AI hardware possible, neuromorphic systems are in need of a low-power, non-volatile and analog memory solution to store the weights of the spiking neural network (SNN). In addition to being used for memory, memristive memory can be read out passively and thus also replaces digital-to-analog circuitry.
In this thesis, two solutions are proposed: one is based on a generalized memristor, the other is based on ferroelectric memory. Both solutions are implemented and simulated in SystemC AMS and tested with a SNN. As a final test, both memory solutions are integrated into a full-sized SNN and simulated against the MNIST dataset. The simulation results validate the capabilities of memristive and ferroelectric memory when it comes to providing a sensible weight storage solution for neuromorphic systems.

Spiking Neural Networks use Address Event Representation to communicate among different Neuron Arrays. To mimic the behavior of the human neural system and meets the requirement for large Neuron Array communication, the AER interconnect should be area-saving, have low power, and operates at high speed.
This thesis aims to build self-timed interconnects for point-to-point and multi-array communication. The whole system is designed at the RTL level using SystemVerilog. For point-to-point communication, two transmitters are implemented and compared according to their synthesis results. In the multi-array communication structure, we develop a generalized segmented-bus topology and the element - Fence to control its segments. Different timing problems in the design are analyzed, and corresponding solutions are proposed. The whole system can operate at around 1Gbps in a self-timed manner without
any timing problems.

Convolutional Neural Networks (CNN) have become a popular solution for computer vision problems. However, due to the high data volumes and intensive computation involved in CNNs, deploying CNNs on low-power hardware systems is still challenging.
The power consumption of CNNs can be prohibitive in the most common implementation platforms: CPUs and GPUs. Therefore, hardware accelerators that can exploit CNN parallelism and methods to reduce the computation burden or memory requirements are still hot research topics. Quantization is one of these methods. One suitable quantization strategy for low-power deployments is logarithmic quantization.

Logarithmic quantization for Convolutional Neural Networks (CNN): a) fits well typical weights and activation distributions, and b) allows the replacement of the multiplication operation by a shift operation that can be implemented with fewer hardware resources.
In this thesis, a new quantization method named Jumping Log Quantization (JLQ) is proposed. The key idea of JLQ is to extend the quantization range, by adding a coefficient parameter "s" in the power of two exponents ($2^{sx+i}$).

This quantization strategy skips some values from the standard logarithmic quantization. In addition, a small hardware-friendly optimization called weight de-zeroing is proposed in this work. Zero-valued weights that cannot be performed by a single shift operation are all replaced with logarithmic weights to reduce hardware resources with little accuracy loss.

To implement the Multiply-And-Accumulate (MAC) operation (needed to compute convolutions) when the weights are JLQ-ed and de-zeroed, a new Processing Element (PE) have been developed. This new PE uses a modified barrel shifter that can efficiently avoid the skipped values.
Resource utilization, area, and power consumption of the new PE standing alone are reported. Resource utilization and power consumption in a systolic-array-based accelerator are also reported.
The results show that JLQ performs better than other state-of-the-art logarithmic quantization methods when the bit width of the operands becomes very small.

To support the spike propagates between neurons, neuromorphic computing systems always require a high-speed communication link.
Meanwhile, spiking neural networks are event-driven so that the communication links normally exclude the clock signal and related blocks. This thesis aims to develop a self-timed off-chip interconnect system with ring topology that supports multi-point communication in neuromorphic computing systems. This interconnect system is implemented in high-level modeling with SystemC and involves the burst-mode two-wire protocol in point-to-point communication. In order to ensure the flexibility of the system, the distributed control system is involved. Further, the system can be configured with different numbers of chiplets to fulfill various spiking neural network structures. We also explore optimization methods, which is a bi-directional ring topology achieving the growth of throughput. Based on evaluation and simulation results, the interconnect system can achieve 4.302Gbps with the specific application scenario.

In the recent past, real-time video processing using state-of-the-art deep neural networks (DNN) has achieved human-like accuracy but at the cost of high energy consumption, making them infeasible for edge device deployment. The energy consumed by running DNNs on hardware accelerators is dominated by the number of memory read/writes and multiplyaccumulate (MAC) operations required. As a potential solution, this work explores the role of activation sparsity in efficient DNN inference. As the predominant operation in DNNs is matrix-vector multiplication of weights with activations, skipping operations and memory
fetches where (at least) one of them is zero can make inference more energy efficient. Although spatial sparsification of activations is researched extensively, introducing and exploiting temporal sparsity is much less explored in DNN literature. This work presents a new DNN layer (called temporal delta layer) whose primary objective is to induce temporal activation sparsity during training. The temporal delta layer promotes activation sparsity by performing delta operation facilitated by activation quantization and l1 norm based penalty to the cost function. During inference, the resulting model acts as a conventional quantized
DNN with high temporal activation sparsity. The new layer was incorporated as a part of the standard ResNet50 architecture to be trained and tested on the popular human action recognition dataset (UCF101). The method caused 2x improvement in activation sparsity, with 5% accuracy loss.

As we move towards edge computing, not only low power but concurrently, critical timing is demanded from the underlying hardware platform. Spiking neural networks ensure high performance and low power when run on specialized architectures like neuromorphic hardware. However, the techniques in use to configure these neural networks on massively parallel neuromorphic crossbar arrays remain sparsely explored. This motivates the research on how neural network topologies encompassing spiking architectures can be configured on a neuromorphic hardware. In this thesis, a unique placement algorithm is devised to map diverse and complex neural network architectures on a connectivity-constrained array with thousands of processing elements(PEs) within seconds. Wide spectra of SNNs with varying complexity are investigated to evaluate the feasibility of mapping on the target neuromorphic architecture involving unique connectivity constraints. The performance of the proposed ALAPIN mapper is validated through time-to-solution for the surveyed SNN schemes with varying network sizes and diverse complexity measures. Experiments show that simple networks converge within 10 milliseconds. With limited resources and as the network architectural complexity increases, hardware constraints become overwhelming to achieve placement solution within a decent time frame. Further experiments are carried out to estimate the resource utilization of each candidate SNN for varying network sizes on target hardware. Liquid state machines use a greater number of synapses for a same number of neurons than the rest of the candidates, with approximately 100% neurons, 30% input resources, and 20% synapses on target hardware.

Neuromorphic electronic systems have used asynchronous logic combined with continuous-time analog circuits to emulate neurons, synapses, and learning algorithms. It is attractive because of its low power consumption and feasible implementation. Typically, the neuron firing rates are lower than the modern digital systems. Thus, the endpoints of neuromorphic electronic systems are clusters of neurons instead of individual neurons. Address event representation (AER) was proposed in 1991 to multiplex communication for a cluster of neurons into an individual communication channel. AER circuits provide multiplexing/demultiplexing functionality for spikes that are asynchronously generated by/delivered to an array of individual neurons. Asynchronous techniques are not only used in neuromorphic electronic systems, but also widely used in globally asynchronous and locally synchronous (GALS) SoCs, or SoCs with full-asynchronous solutions. However, commercial tools on the market do not support designing asynchronous circuits, making the circuits cannot be adopted easily by most products. This thesis aims at addressing the challenge by providing an asynchronous library establishment strategy. The strategy uses SR-latches as standard asynchronous cells together with logic gates to build an AER communication circuit. With the strategy, the performance of using a modified traditional arbiter in the AER transmitter can be compared favourably with using state-of-the-art arbiters. A back-end flow and a verification flow are developed to evaluate the performance of the design as well as to check the feasibility of the strategy. The proposed 32-bit AER transmitter under TSMC 28nm CMOS technology sacrifices area and power to achieve better timing performance, where the modified arbiter inside has an 11.54% better response time than the arbiter who used to be the best in an old comparison.

Conversion from digital information to spike trains is needed for Spiking Neural Networks. Moreover, it is one of the most important steps for Spiking Neural Networks. This conversion could lead to much information loss depending on which encoding algorithm is used. Another major problem that can occur in a specific use-case is the limited bandwidth for the spikes that get generated through the encoding algorithm. In this thesis, we propose population Step Forward Encoding algorithm. This algorithm takes the signal encoding accuracy of Step Forward encoding algorithm and makes it into a population, generating multiple spike trains. This allows a higher threshold to encode a large part of the signal, increasing the efficiency. We show that population Step Forward Encoding algorithm doesn't just work good for the signal encoding accuracy, but also for the classification accuracy. Moreover, population Step Forward Encoding algorithm does not only have a high efficiency with a low spike count, it can also achieve higher efficiency with higher spike count. Thus, population Step Forward can make most use of a limited bandwidth of spikes.

Advanced automotive vehicles are based on the real-time fusion of an increasing number of automotive sensors. For precise fusion of different sensors, measurements need to be synchronized both temporally and spatially. This thesis aims to design a hardware temporal synchronization block as part of the PRISTINE systolic array accelerator project for multi-sensor data fusion. In this process, we study and address several temporal sensor synchronization issues that are characteristic of the considered system as well as any other typical sensor fusion system. First and foremost, we handle the problem of estimating the actual time of sensor measurement by exploring well-known filtering techniques such as Kalman, mean and median filters. A suitable filter is selected for implementation based on the statistical characteristics of the observed sensor cycle times, the complexity of the filters and the quality of obtained estimates. Next, we address the issue of reconstructing incoming sensor data streams according to the estimated sensor measurement times while maintaining minimal latency and synchronization error by employing an adaptive stream buffering technique utilized in distributed multimedia systems. An analysis of the effects of the stream synchronization algorithm's parameters on buffering latency and synchronization error was presented. Finally, the above synchronization solution was efficiently implemented on hardware by making certain modifications and design decisions to the algorithm. A method to evaluate the whole temporal synchronization process is proposed and the obtained results on real sensor data are presented.

DTB Multiplexer is a component within an NXP chip called the BAP3. This component provides a testing functionality for the chip. This component is purely combinational, and requires no clock, however this makes the component wiring-costly. This high wiring requirement leads to the area constraint imposed by the wiring demand rather than cell area, and this also leads to the DTB multiplexer reducing the placement area available for other modules. In this thesis, the wiring area is going to be estimated as the amount of congestion, which would cause detour in the design which results in extra wiring. In this thesis, DTB multiplexer is placed by external method instead of using the place and route tools usually used by the design team. Instead, the placement is done on MATLAB which is later ported to the place and route tools using script. The placement algorithm implemented in MATLAB is primarily based on two algorithm, Dplace for initial preplacement, which in turn utilizes diffusion preplacement algorithm, and modified C-ECOP for the congestion reduction. More detailed congestion estimation done by using an additional routing estimation algorithm which is based on One-Steiner routing algorithm. The result indicates that the modified C-ECOP can be used to reduce congestion, thus wiring area when paired with a good initial placement algorithm, but the initial placement algorithm and detailed congestion estimation algorithm with one-steiner could be further improved, and further work is needed to integrate the result with commercial

The international community firmly recognizes cyber-attacks as a serious fear that could endanger the global economy. The Global Risks 2015 report, published by the World Economic Forum, included this rather strong warning: “90 percent of companies worldwide recognize that they are insufficiently prepared to protect themselves against cyber-attacks”. Even worse, the Center for Strategic and International Studies estimates that cyber attacks and cybercrime already cost the global economy over US$400 billion per year! Attacks are likely to increase in size and to diversify in nature, driven by the expanding number of services available online and the increasing sophistication of cyber criminals who are engaged in a cat-and-mouse game with security experts. The impact of attacks can even be catastrophic when it comes to critical infrastructures such as power grids and nuclear plants. Hence, there is an urgent need for robust solutions.

Developing appropriate solutions requires a deep understanding of potential and/or existing attacks; these can have either a hardware or a software nature. As the state-of-the-art provides some good solutions for software attacks, hackers seem to move recently more to the exploration of hardware as a powerful mean of attacks. Examples of such attacks are fault injection, side channel analysis, and hardware Trojans. Among these, side channel attacks are recognized as powerful attacks as they do not require any insertion to the system (i.e., they are purely based on observations), making them undetectable. Side channel attacks come in many flavors; one of the most popular is the template-based power attack. In this case, the adversary uses an identical copy of the targeted device and performs a physical characterization to extract a profile of the device which is used later during the attack. As this step is very complex, hackers are trying to use deep learning for the physical characterization. Providing a solution against such attacks needs a deep and full understanding of such attack. This thesis explores the usage of deep learning as a way to advance the accuracy of the side channel attack. Two scenarios are developed and experimented with: one based on supervised learning and one on unsupervised learning. In the supervised scenario, the attacks are enhanced using data pre-processing, which improves the classification accuracy of the associated physical characterization method based on Convolutional Neural Network (CNN). In the unsupervised scenario, the attacks are trying to skip part of the physical characterization (called profiling) and apply clustering using Stacked Autoencoder neural network in order to retrieve potential secret information. The two scenarios are implemented and validated against the two of the most widely used cryptographic algorithms known as Advance encryption standard (AES) and Elliptic Curve Cryptography (ECC). The results show the usage of data pre-processing techniques increases the accuracy of attacks by 30% and 15% on AES software and hardware implementations, respectively. The results of the clustering model show that it is feasible to advance the power attacks by skipping the characterization/profiling phase. The results show a 60% prediction accuracy for both aligned and misaligned power traces of the ECC implementations.

This thesis proposes a low-cost high-efficiency source-synchronous interface for high-speed inter-chip communication. The interface is composed of LVDS transceivers as external I/O buffers, and an all-digital data recovery, which can calibrate the received data phase to be aligned to the 90^◦ phase of the received half-rate reference clock, for error free data sampling. The proposed data recovery adopts a full-digital scheme, which uses time-to-digital converters (TDC) as phase acquisition, a digitally-controlled delay line (DCDL) to calibrate the phase, and a finite-state machine (FSM) as the control unit. Reference clock generated from phase-locked loops (PLL) or delay-locked loops (DLL) is not needed for the proposed data recovery. The interface is implemented in UMC 65 nm Low-leakage technology, with circuits designed at both transistor-level and RTL-level. The post-layout simulation shows the proposed interface works properly with data rates from 412.4Mbps to 1.25Gbps in all process corners. The total layout area is 688 x 87 µm, and the total power consumption is 16.74 mW. 

Partial Discharges(PD) are commonly produced in defects within the insulation systems of high voltage equipment. These discharges are typically nanosecond current pulses in the amplitude range of milli-amperes. A long term exposure of the insulation system to these partial discharges accelerate the aging mechanisms that eventually lead to the final breakdown of the insulation system. Such insulation breakdowns in High Voltage (HV) / Medium Voltage (MV) equipment typically involve arc-flash/fire hazards, posing safety threats. Moreover probable undelivered power and huge financial losses are also associated. Early detection of PD activity can provide warnings about pending insulation/device failures and hence, maintenance or repair activities can be scheduled before breakdown occurs. Moreover, clustering of PD due to different types of sources is of practical importance as it indicates the severity of defect and provides an insight into the time available for repair activities before complete breakdown. State of the art tools for electrical PD monitoring are expensive and cannot be economically deployed over a large network of HV/MV assets. Moreover, they employ classification schemes based on less robust PD features. This thesis marks the completion of the first stage in the process of building an open source, cost-effective, automated embedded online partial discharge detection tool for feature extraction and PD classification based on new, advanced robust features of partial discharges. As an outcome of this thesis, an embedded solution for real time PD detection and feature extraction was developed to facilitate future PD classification.