Self-timed interconnect for SNN - From Point to Point Communication to Multi-array Segmented-bus Solution

Master thesis (2022)

Authors

J. Zhang Electrical Engineering, Mathematics and Computer Science

Contributors

T.G.R.M. van Leuken Signal Processing Systems - EEMCS (mentor)
N.K. Mandloi Signal Processing Systems - EEMCS (graduation committee member)
Faculty
Electrical Engineering, Mathematics and Computer Science, Electrical Engineering, Mathematics and Computer Science
Copyright: © 2022 Jinyao Zhang
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Published Date

30-11-2022

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Abstract

Spiking Neural Networks use Address Event Representation to communicate among different Neuron Arrays. To mimic the behavior of the human neural system and meets the requirement for large Neuron Array communication, the AER interconnect should be area-saving, have low power, and operates at high speed.
This thesis aims to build self-timed interconnects for point-to-point and multi-array communication. The whole system is designed at the RTL level using SystemVerilog. For point-to-point communication, two transmitters are implemented and compared according to their synthesis results. In the multi-array communication structure, we develop a generalized segmented-bus topology and the element - Fence to control its segments. Different timing problems in the design are analyzed, and corresponding solutions are proposed. The whole system can operate at around 1Gbps in a self-timed manner without
any timing problems.

Files

MSc_JinyaoZhang_Thesis.pdf
(pdf | 1.89 Mb)
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