This study deals with the challenge of warpage in power modules, vital components in the rapidly expanding electric and hybrid-electric vehicle industry. The variations in temperature during manufacturing, resulting in significant warpage changes, contribute to device cracks, delamination, and reduced reliability.
The primary focus is understanding and mitigating the warpage phenomenon in power module substrates. This warpage is induced by thermo-mechanical stresses during the assembly packaging process. The investigation begins by exploring the cause of warpage change by characterizing annealed copper properties and employing 2D finite element model (FEM) analysis. The study identifies plastic strain as the dominant cause of warpage change during process steps. Subsequently, a validated 3D FEM simulation model is developed to replicate practical annealing and sintering processes. Lastly, the project delves into factor analysis to identify critical variables influencing warpage. It underscores that balancing residual copper volume is crucial in warpage reduction. Additive and subtractive manufacturing techniques establish a correlation between the removal of copper volume and warpage reduction.

This project provides comprehensive insights into the manufacturing process of AMB substrate, warpage behavior, and effective strategies for reduction, constructing a solid foundation for future manufacturing and design.

Power electronics are an important technology used to convert electricity from a source like a battery or high voltage DC bus to more usable forms of electricity. This has to be done efficiently, reliably and without failures which is critical in applications like electric cars or datacenters. Power MOSFETs with upcoming SiC and GaN devices are an important building block used in these converters. Hence these power MOSFET devices have to be improved continuously to get a lower on resistance (R_DSon), a better thermal dissipation and lower parasitic losses. In this thesis we will take a look at the embedding of power MOSFETs inside a PCB to obtain these improvements. This new technology needs to be evaluated in terms of reliability, failure-modes and thermal/electrical performance. By designing,
manufacturing and testing a PCB with embedded devices. During manufacturing silver sintering has been used for attaching the die to a copper coin. In the end the manufacturing has been done successfully.
Testing showed an 18% lower R_DSon and a twice as low junction to ambient thermal impedance indicating a better performance compared to regular packaging.

Today’s cars are undergoing the greatest transformation the industry has seen. Power MOSFETs play a crucial role in making electronics more energy efficient by driving down switching losses and Rdson using a combination of next-generation trench technology and ultra-thin dies. Power MOSFET dies are becoming larger ( > 5 X 5 mm ) and thinner ( < 50 μm ) to meet the high performance lifetime requirements of the automotive industry. The high aspect ratio and the new chip designs with trench technology offer challenges for assembly, packaging and testing.

The majority of the research performed in the past, aimed to reduce the risk of die crack by improving equipment and process strategies in back-end semiconductor processing. This thesis study aims at improving die
strength from a front-end approach (device fabrication process) by making dies stronger to stress from die frontside. New chip designs are presented with new metal layer layouts for improved stress distribution. Materials like polyimide are investigated as new die top material for mechanical strengthening of die frontside. Key factors which influence die strength like trench-metal interaction, wafer stress and warpage are also analyzed in this thesis report.

In this study, ultra-thin power MOSFET dies are realised on 100 mm diameter silicon wafers with dimensions of 6 X 3 X 0.050 mm. These dies are mechanical equivalent in design, robustness to commercial trench power MOSFETs. The processed wafers are grinded from the backside to realise 50 μm thin wafers which are then sawned to obtain singulated dies. The strength of the dies are characterized by three-point bending tests and analyzed using probability plots for weibull distribution.

This project, is aimed at making a device with TSVs (through silicon VIAs) interconnections using a new method based on vacuum filling with conductive nano-copper paste and by testing different diameter sizes and finding the best method and procedure for the fabrication of the chip.
Second ambition is filling the TSV interconnections, with a new and promising material (nano copper paste particles), which is expected to have excellent conductivity and electrical properties, by utilizing a new TSV filling method. Copper, because of having great electrical properties such as conductivity and due to its low expense rather than other materials such as gold and silver, and even though of its high oxidation weakness, is still the currently used material for interconnections in the microelectronics
field.
However, reliable, environmental friendly, and low temperature interconnects rely on the exceptional properties of Metallic Nanoparticle Pastes (MNPs) and recently Copper nanoparticles are investigated as interconnect material. It is possible to combine this nano paste particle usage by microfabrication and lithography and optimizing the fine pitch vertical interconnection by using this promising material. The copper nanoparticles paste used in this project is
CUAN-TUMFUSE, 22.2g SN: 16035. The method used during this project for TSVs filling is a new method by utilizing the Vacuum air machine which sucks the air from one side and pulls out the air from an other side.