A thorough understanding of the small-signal response of solar cells can reveal intrinsic device characteristics and pave the way for innovations. This study investigates the impedance of crystalline silicon PN junction devices using TCAD simulations, focusing on the impact of frequency, bias voltage, and the presence of a low–high (LH) junction. It is shown that the PN junction exhibits the behavior of a parallel resistor–capacitor circuit (RC-loop) with fixed element values at low frequencies, but undergoes relaxation in both resistance R_j and capacitance C_j as frequency increases. Moreover, it is revealed that the addition of a LH junction impacts the impedance by altering R_j, C_j, and the series resistance R_s. Finally, while various publications on solar-cell impedance model the LH junction using an RC-loop, the findings in this study indicate that such a model does not accurately represent the underlying physics. Instead, this approach is likely compensating for the frequency-dependent behavior of R_j and C_j.

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Photovoltaic modules are typically not optimized for conditions of partial shading. One proposed approach to improve their shade tolerance is to implement maximum power point tracking on different strings of cells within the modules. However, this approach increases the demand for sub-module power converters, which poses a challenge. To address this, researchers have suggested integrating power electronic components directly into the module laminate, or even within the solar cells themselves. Despite these advancements, limited research has focused on integrating the most bulky component: the inductor. This study investigates through simulations whether planar air-core inductors can yield the required properties to support sub-module power conversion. The simulated inductors have an area that is as large as an industrial crystalline silicon solar cell. First, it is shown how the interplay between the different design parameters, such as track spacing, track width, number of turns, and middle gap size, plays an important role in the inductor properties at high frequency. The coil geometries that are simulated yield inductance values between 0.3 μH and 3.2 μH. Subsequently, the feasibility of implementing these inductors into an exemplary DC–DC boost converter is evaluated. To adequately reduce the ripple current, a significant switching frequency of at least several hundred kHz is required. Additionally, at 500 kHz, an inductor thickness of around 0.5 mm is necessary to keep the ohmic losses in the inductor below 2% of the total generated power in standard test conditions. While demonstrating feasible combinations, these findings also present significant challenges.@en

Power electronics (PE) plays a crucial role in optimizing the performance of photovoltaic (PV) systems. At present, module and sub-module level PE is increasingly being adopted in global PV installations. Typically, PE for sub-module purposes is installed in the PV junction box. However, in this dissertation another approach is investigated: integrating power electronics into or onto crystalline silicon (c-Si) PV cells. This approach has the potential to contribute to the development of shade-tolerant PV modules, increase the reliability of PV module-integrated PE, reduce the volume and weight of the PV system, and support the development of autonomous devices powered by low-power and low-current PV cells. Specifically, the aim of this dissertation is to study the integration of different PE components into c-Si solar cells, and identify the most promising approaches. The dissertation is structured in two parts.

In Part 1, the objective is to gain a comprehensive understanding of the impedance of c-Si solar cells. To this end, Chapter 2 reports a characterization of the impedance of eight single-cell laminates. Each laminate contains a different commercially available c-Si solar cell, featuring various cell architectures, namely Aluminium Back Surface Field (Al-BSF), Passivated Emitter and Rear Contact (PERC), Tunnel Oxide Passivated Contact (TOPCon), Interdigitated Back Contact (IBC), and Silicon Heterojunction (SHJ). It is found that the two main factors contributing to a high PN junction capacitance (C_j) at maximum power point (MPP) are (1) a low wafer dopant concentration and (2) a high MPP voltage. Furthermore, the studied cell laminates exhibit inductances between 63 and 130 nH. Following this, the impedance of PN junctions is further investigated in Chapter 3. Specifically, PN homojunction devices are investigated through Technology Computer-Aided Design (TCAD) simulations. This methodology allows to study the junction impedance in a detailed way, which may be difficult to do experimentally due to noise and reactance of metal contacts. Through analysis of the impedance data it is revealed that the PN junction exhibits the behaviour of a parallel resistor-capacitor circuit (RC-loop) at low frequencies, but undergoes relaxation in both PN junction resistance R_j and capacitance C_j as frequency increases. While various publications on solar-cell impedance model the low-high (LH) junction using an RC-loop, the findings presented in this chapter indicate that such a model does not accurately represent the underlying physics. Instead, this approach is likely compensating for the frequency-dependent behavior of R_j and C_j. Finally, in Chapter 4, the PN junction impedance of modern c-Si solar cells is studied across varying temperature and illumination conditions. In the tested conditions, the range in which the area-specific MPP R_j varies is similar for different cell architectures, despite their different properties. Conversely, the range in which the areal MPP C_j varies is significantly affected by the substrate dopant concentration and MPP voltage of the cell.

In Part 2, the aim is to assess the feasibility of leveraging solar-cell impedance at the input of a power converter, and to explore various methods for integrating additional PE components into solar cells. In Chapter 5, the feasibility of integrating different PE components into c-Si solar cells is explored. First of all, diodes exhibit high ease of integration into PV cells and successfully integrated designs have already been demonstrated in prior work. Alternatively, the integration of transistors is more complex. Since transistor fabrication processes require lithographic steps, it is necessary for cost-effective integration to combine as many processing steps as possible with PV fabrication. Regarding passive component integration, it is found that the self-capacitance of modern c-Si solar cells is sufficiently large to replace the input capacitor of an exemplary boost converter. However, for thin-film capacitor integration, it is challenging to achieve a sufficiently high areal capacitance. Moreover, the self-inductance of a solar-cell string could potentially be leveraged to replace the inductor at the input of a power converter. By analyzing this approach for an exemplary boost converter, it was found that high switching frequencies in the MHz range are required. Alternatively, the required switching frequency may be reduced through the integration of planar inductors. It was found that the area of PV cells is sufficiently large to facilitate the integration of planar coils exhibiting inductance values that are useful for power conversion. Finally, general challenges that should be considered for successful PE-PV integration are appropriate thermal management, opto-electric behaviour under illumination, and repairability. The inductor integration is further studied in Chapter 6. Specifically, it is explored whether large-area planar air-core inductors can yield the required inductor properties to support sub-module power conversion in PV modules. First, it is shown how the interplay between the different design parameters, such as track spacing, track width, number of turns, and middle gap size, play an important role in the inductor properties. This analysis includes changes due to high-frequency effects, which significantly impact the results. The coil geometries that are simulated yield inductance values between 0.3 and 3.2 μH. Considering the power losses, the applicability of such inductors in sub-module power converters is discussed. Finally, in Chapter 7, the concept of COSMOS (COmbined Solar cell and MOSFET) devices is introduced and a process flow is proposed in which back-contact TOPCon solar cells and lateral power MOSFETs are simultaneously fabricated on a single substrate. This process is successfully employed to manufacture both n-type solar cells with integrated p-channel MOSFETs (PMOS) and p-type solar cells with integrated n-channel MOSFETs (NMOS). Notably, efficiencies exceeding 20% are achieved for both n-type and p-type solar cells, highlighting the potential of COSMOS solar cells. Furthermore, two main integration challenges are identified. Firstly, the off-state leakage currents of the MOSFETs increase due to illumination. Secondly, specific topologies of monolithic integration lead to increased off-state leakage currents.@en

The impedance of solar cells can be leveraged for a variety of innovative applications. However, for the continued advancement of such applications, it is crucial to understand how the impedance varies during practical operation. This work characterizes the impedance of modern crystalline silicon solar cells across different bias voltages and under varying illumination and temperature conditions. It is found that for a given bias voltage, variations in temperature have a notably stronger impact on PN junction impedance than changes in irradiance. However, during maximum power point (MPP) tracking, variations in irradiance have a larger influence on the PN junction impedance than temperature variations. This is related to the shifting operating voltage during operation. Furthermore, it is shown that the capacitance during practical operation can strongly vary for different solar cells. For instance, the areal MPP capacitance values of the two cells tested in this study at 0.1 sun irradiance and a temperature of 30 °C were 0.283 μF/cm2 and 20.2 μF/cm2, a 71-fold difference. Conversely, the range of the MPP diffusion resistance was found to be highly similar for different cells. The results of this study enhance the understanding of solar-cell impedance and have a broad applicability.@en

Nowadays, an increasing share of photovoltaic (PV) systems makes use of module- or submodule-level power electronics (PE). Furthermore, PE is used in stand-alone devices powered by PV-storage solutions. One way to facilitate further implementation of PE in PV applications is to integrate PE components into crystalline silicon PV cells. Herein, the COSMOS device is introduced, denoting COmbined Solar cell and metal-oxide-semiconductor field-effect transistor (MOSFET). Specifically, the combined manufacturing of lateral power MOSFETs and interdigitated back contact solar cells with tunnel-oxide passivated contacts (TOPCon) on a single wafer is reported. Many steps of the proposed process flow are used for the fabrication of both devices, enabling cost-effective integration of the MOSFET. Both n-type solar cells with integrated p-channel MOSFETs (PMOS) and p-type solar cells with integrated n-channel MOSFETs (NMOS) are successfully manufactured. NMOS devices perform better in achieving low on-resistance, while PMOS devices exhibit lower leakage currents. Furthermore, the study reveals integration challenges where off-state leakage currents of the MOSFET can increase due to illumination and specific configurations of monolithic interconnections between the MOSFET and the solar cell. Nevertheless, for both n-type and p-type solar cells, efficiencies exceeding 20% are achieved, highlighting the potential of the proposed process for COSMOS devices.

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To achieve a high performance in sub-module power conditioning circuits, it is important that power converters are designed in accordance with the photovoltaic (PV) cell impedance at the input. Taking this one step further, exploiting the impedance of cell strings could even support novel power conditioning approaches in PV modules. In this work, we characterize the impedance of eight single-cell laminates based on different industrial c-Si PV cell architectures. This characterization is carried out by impedance spectroscopy in dark conditions at room temperature, and the capacitive and inductive effects are evaluated through equivalent model fitting. By comparing the results for the different laminates, it is revealed how the cell design affects its impedance. Our experiments show that the PN junction capacitance at maximum power point varies for the different cells between 0.30 and 45.6 μF/cm². The two main factors contributing to a high PV cell capacitance at maximum power point are (i) a low wafer dopant concentration and (ii) a high maximum power point voltage. In high-efficiency c-Si PV cells that will be fabricated in the coming years, increasing capacitances are expected for operation near the maximum power point. Furthermore, the single-cell laminates exhibit inductances between 63 and 130 nH, and our results indicate that the inductance is mostly affected by the number of busbars and the geometry of the metal contacts.

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Surface textures that result in high optical yields are crucial for high efficiency photovoltaic (PV) devices. In this work three different texturing approaches are presented that result in smooth concave structures devoid of sharp features. Such features can sustain the crack-free growth of device quality nano- to poly-crystalline materials such as nano-crystalline silicon, perovskites or C(I)GS, facilitating routes towards hybrid multijunction PV devices. A sacrificial implanted poly-c-Si layer is used to develop a random surface texture for the first texturing approach (Tsac). The influence of the processing conditions, such as layer thickness, implantation energy, dose and ion type, annealing time and temperature, of the sacrificial layer on the developed surface features is investigated. Additionally, a photolithographically developed honeycomb texture (Thoney) is presented. The influence of mask design on the honeycomb features is discussed and a relation is established between the honeycomb period and crack formation in nano-crystalline silicon layers. The reflective properties (spectral reflection, haze in reflection and angular intensity distribution) of these approaches are characterized and compared to a third texturing approach, Tsp, the result of chemically smoothened pyramidal <111> features. It was demonstrated that high optical scattering yields can be achieved for both Thoney and Tsp. Additionally, the performance of a-Si/nc-Si tandem devices processed onto the different textures is compared using both optical device simulations and real device measurements. Simulations demonstrate strong improvements in Jsc-sum (≈45%), in reference to a flat surface, and high Voc*FF of over 1 V are demonstrated for Tsp.@en

Power electronics traditionally plays a crucial role in conditioning the power of photovoltaic (PV) modules and connecting the systems to the electricity grid. Recently, PV module designs with more sub-module power electronics are gaining increased attention. These designs can offer higher reliability and improved resilience against non-uniform illumination. In this review, we explore an innovative method to facilitate sub-module power electronics, which is to integrate the power components into crystalline silicon (c-Si) PV cells. This approach has the potential to enable numerous design innovations. However, the fabrication processes of the integrated power electronics should be compatible with the PV cell fabrication methods. Moreover, only a limited amount of additional processing steps can be added with respect to standard solar cell manufacturing processes to achieve a cost-effective design. After reviewing previous research on this topic, we propose various new design possibilities for PV-cell-integrated diodes, transistors, capacitors, and inductors. Furthermore, we discuss the technical trade-offs and challenges that need to be overcome for successful industry adoption.

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Two terminal multi-junction (MJ) photovoltaic (PV) devices are well established concepts to increase the solar-to-electrical power conversion in reference to single PV junctions. In multi-junction PV devices two consecutive sub-cells are interconnected using a tunnel recombination junction (TRJ) in which the light excited holes of one sub-cell recombine with the light excited electrons of the other sub cell. An ideal TRJ is an ohmic contact with non-rectifying behaviour. TRJ's based on p- and n-doped silicon-oxides have been successfully applied in a variety of hybrid multi-junction PV devices in which tunnelling and trap-assisted tunnelling over width of 5–20 nm rules the TRJ's recombination kinetics. In this contribution the qualitative fundamental working principles of tunnel recombination junctions based on p- and n-doped silicon and silicon-oxide alloys are revealed using both electrical modelling and experiments based on a unique set of tandem lab cells (four types based on four different PV materials) combined with structural variations in TRJ architectures. The study results in design rules for the integration of silicon-oxide based TRJ's and provides fundamental insights into the sensitivity of the electrical performance of the TRJ's to doping concentrations, to alignment of the conduction and valence bands of consecutive sub-cells, to the nature of interface defects, to the growth of amorphous and crystalline phases and its dependence on substrate or seed layers and to the nanoscale thicknesses of the TRJ layers.

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A logical next step for achieving a cost price reduction per Watt peak of photovoltaics (PV) is multijunction PV devices. In two-terminal multijunction PV devices, the photo-current generated in each subcell should be matched. Intermediate reflective layers (IRLs) are widely employed in multijunction devices to increase reflection at the interface between subcells to enhance current generation in the subcell(s) positioned before the IRL, in reference to the incident light. In this work, the results of over 65 multijunction devices are presented, in order to explore the effect of different current matching approaches. The influence of variations in absorber thickness as well as thickness variations of different IRLs based on silicon-oxide, various transparent conductive oxides (TCO), and metallic layers on all-silicon multijunction PV devices is studied. Specifically, hybrid, 2-terminal, monolithically integrated silicon heterojunction (SHJ) and thin film nanocrystalline silicon (nc-Si:H) and amorphous silicon (a-Si:H) tandem and triple junction devices are processed. Based on these experiments, certain design rules for optimal current matching operation in multijunction devices are formulated. Finally, taking these design rules into account, record all-silicon multijunction devices are processed. Conversion efficiencies close 15% and (Formula presented.) V are demonstrated for triple junction SHJ/nc-Si:H/a-Si:H devices. Such conversion efficiencies for a wireless, high-voltage wafer-based all-silicon 2-terminal multijunction PV device opens the way for efficient autonomous solar-to-fuel synthesis systems as well as other wireless innovative approaches in which the multijunction solar cell is used not only as a photovoltaic current-voltage generator, but also as an ion-exchange membrane, electrochemical catalysts, and/or optical transmittance filter.

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Tandem photovoltaic (PV) devices are receiving a lot of attention as the next step in PV for further increasing performance in combination with reducing the cost price per Watt peak. The integration of an effective tunnel recombination junction (TRJ) is crucial for efficient multijunction performance. In this work a rigorous and extensive study is presented that reveals the fundamental operating mechanisms that govern the TRJ performance. This is achieved by performing a structural study on the TRJ design in multiple tandem architectures based on different photovoltaic absorber layers. Experimental results are presented of a large number of tandem devices, including SHJ/nc-Si:H, nc-Si:H/a-Si:H, nc-Si:H/a-SiGe:H and a-SiGe:H/a-Si:H, in which the same p-layer design variations are applied. Across these device architectures the influence of the p-layer material properties, p-layer thickness, bilayer configurations and p-doped contact layer properties are investigated, to yield a unique insight into TRJ behavior.

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