Photovoltaic (PV) modules have considerable difficulty when exposed to shading since even partial blockages can significantly reduce energy production. To make the PV module shade-resilience, sub-module maximum power point tracking(MPPT) can be done for each string in the module. One way of doing it is by using converters at the sub-module level, which can track the string's maximum power point(MPP) by varying its duty cycle. In conventional converter design, inductors are the bulkiest and costliest component used, which eventually makes the application of sub-module MPPT less cost-effective. However, a literature study found that solar cell generates self-impedance under biasing, which opens up the idea for cell-level integration of power electronics. This thesis aims to validate the possibility of using the self-inductance generated in the solar cell for partially designing the DC/DC converter on the solar cell such that MPPT can be performed at the sub-module level. To accomplish this objective, two distinct strategies have been examined: The utilization of solar cell self-inductance for designing a conventional boost converter on a solar cell surface and the integration of a planar coil onto a solar cell for partially designing a DC/DC boost converter.

As PV capacity in urban areas keeps increasing, non-uniform illumination of panels will become more prevalent. This could cause the partial shading to become more frequent, reducing PV system performance. Some ways to solve this problem is by the use of module-level maximum power point tracking (MPPT), micro inverters, or reconfigurable modules. To this end, the integration of metal-oxidesemiconductor field-effect transistor (MOSFET) on solar cells could play an important role in future methods to prevent this issue. This integration of a MOSFET allows for module level, and potentially sub-module level, MPPT, as well as the application of reconfigurable modules to circumvent this issue. This thesis aims to optimize the MOSFET dimensions and fabrication process to be able to handle the short circuit current and open circuit voltage of a PV module, and to analyze the optoelectrical effects under direct illumination of the MOSFET performance. In this thesis report, a flowchart is proposed on how to fabricate a working power MOSFET while combining the fabrication techniques used in the Integrated Circuits and Photovoltaics industries. This process closely resembles the fabrication of solar cells and uses similar techniques used to fabricate interdigitated back contacted (IBC) solar cells. It is shown that It is shown that the use of wider devices can reduce channel resistance from 167Ω for a PMOS device with a width of 500𝜇m down to 20Ω for a device with a width of 5000𝜇m. For NMOS devices a similar relationship can be seen where the channel resistance is 49Ω for a width of 500𝜇m and 8.1Ω for a device width of 5000𝜇m. The current density of the devices drop from 115𝜇𝐴/𝜇𝑚 for an NMOS device with a width of 500𝜇m to less than 80𝜇𝐴/𝜇𝑚 for a 5000𝜇m wide device. For PMOS this density drop is smaller where the drop is from 33𝜇𝐴/𝜇𝑚 to 27𝜇𝐴/𝜇𝑚. A study on the effects of implantation energy and scattering layer thicknesses showed that both lower energies and thicker layers yield higher drain currents and lower channel resistance. A possible explanation for this is that a shift in the threshold voltage increased the overdrive voltage and therefore the drain current. In the investigation of the effects of direct illumination on the electrical characteristics of the device it was found that the threshold voltage increases for PMOS devices from -0.21V under no illumination to -0.06V under full spectrum illumination at 1000𝑊/𝑚2 and decreases for NMOS devices from 0.06V under no illumination to -0.15V under full spectrum illumination at 1000𝑊/𝑚2. Furthermore the off state gate leakage current increases by factor 33 under illumination at 1000𝑊/𝑚2 for NMOS devices and by a factor of 107 for PMOS devices. The electron mobility of the NMOS transistor increases with incident light, improving the drain current gate voltage relationship. The channel resistance for the NMOS devices improved between 5-13%, depending on the intensity of the illumination, while the channel resistance of the PMOS increases up to 2%.A similar effect for the hole mobility of the PMOS was not observed. Similarly, the channel resistance of the NMOS transistor improved, possibly due to the shift in threshold voltage or improved electron mobility. This improvement in performance was not recognized for PMOS transistors, however. A flowchart has been proposed for a process in which a MOSFET is fabricated on the backside of an Interdigitated Back Contacted (IBC) solar cell while combining as many steps as possible from their respective flowcharts to reduce complexity and costs, possibly leading the best balance between MOSFET and IBC fabrication.As PV capacity in urban areas keeps increasing, non-uniform illumination of panels will become more prevalent. This could cause the partial shading to become more frequent, reducing PV system performance. Some ways to solve this problem is by the use of module-level maximum power point tracking (MPPT), micro inverters, or reconfigurable modules. To this end, the integration of metal-oxidesemiconductor field-effect transistor (MOSFET) on solar cells could play an important role in future methods to prevent this issue. This integration of a MOSFET allows for module level, and potentially sub-module level, MPPT, as well as the application of reconfigurable modules to circumvent this issue. This thesis aims to optimize the MOSFET dimensions and fabrication process to be able to handle the short circuit current and open circuit voltage of a PV module, and to analyze the optoelectrical effects under direct illumination of the MOSFET performance. In this thesis report, a flowchart is proposed on how to fabricate a working power MOSFET while combining the fabrication techniques used in the Integrated Circuits and Photovoltaics industries. This process closely resembles the fabrication of solar cells and uses similar techniques used to fabricate interdigitated back contacted (IBC) solar cells. It is shown that It is shown that the use of wider devices can reduce channel resistance from 167Ω for a PMOS device with a width of 500𝜇m down to 20Ω for a device with a width of 5000𝜇m. For NMOS devices a similar relationship can be seen where the channel resistance is 49Ω for a width of 500𝜇m and 8.1Ω for a device width of 5000𝜇m. The current density of the devices drop from 115𝜇𝐴/𝜇𝑚 for an NMOS device with a width of 500𝜇m to less than 80𝜇𝐴/𝜇𝑚 for a 5000𝜇m wide device. For PMOS this density drop is smaller where the drop is from 33𝜇𝐴/𝜇𝑚 to 27𝜇𝐴/𝜇𝑚. A study on the effects of implantation energy and scattering layer thicknesses showed that both lower energies and thicker layers yield higher drain currents and lower channel resistance. A possible explanation for this is that a shift in the threshold voltage increased the overdrive voltage and therefore the drain current. In the investigation of the effects of direct illumination on the electrical characteristics of the device it was found that the threshold voltage increases for PMOS devices from -0.21V under no illumination to -0.06V under full spectrum illumination at 1000𝑊/𝑚2 and decreases for NMOS devices from 0.06V under no illumination to -0.15V under full spectrum illumination at 1000𝑊/𝑚2. Furthermore the off state gate leakage current increases by factor 33 under illumination at 1000𝑊/𝑚2 for NMOS devices and by a factor of 107 for PMOS devices. The electron mobility of the NMOS transistor increases with incident light, improving the drain current gate voltage relationship. The channel resistance for the NMOS devices improved between 5-13%, depending on the intensity of the illumination, while the channel resistance of the PMOS increases up to 2%.A similar effect for the hole mobility of the PMOS was not observed. Similarly, the channel resistance of the NMOS transistor improved, possibly due to the shift in threshold voltage or improved electron mobility. This improvement in performance was not recognized for PMOS transistors, however. A flowchart has been proposed for a process in which a MOSFET is fabricated on the backside of an Interdigitated Back Contacted (IBC) solar cell while combining as many steps as possible from their respective flowcharts to reduce complexity and costs, possibly leading the best balance between MOSFET and IBC fabrication. As PV capacity in urban areaskeeps increasing, non-uniform illumination of panels will become more prevalent.This could cause the partial shading to become more frequent, reducing PVsystem performance. Some ways to solve this problem is by the use ofmodule-level maximum power point tracking (MPPT), micro inverters, orreconfigurable modules. To this end, the integration ofmetal-oxidesemiconductor field-effect transistor (MOSFET) on solar cells couldplay an important role in future methods to prevent this issue. Thisintegration of a MOSFET allows for module level, and potentially sub-modulelevel, MPPT, as well as the application of reconfigurable modules to circumventthis issue. This thesis aims to optimize the MOSFET dimensions and fabricationprocess to be able to handle the short circuit current and open circuit voltageof a PV module, and to analyze the optoelectrical effects under directillumination of the MOSFET performance. In this thesis report, a flowchart isproposed on how to fabricate a working power MOSFET while combining thefabrication techniques used in the Integrated Circuits and Photovoltaicsindustries. This process closely resembles the fabrication of solar cells anduses similar techniques used to fabricate interdigitated back contacted (IBC)solar cells. It is shown that It is shown that the use of wider devices canreduce channel resistance from 167Ω for a PMOS device with a width of 500𝜇m down to 20Ω for a devicewith a width of 5000𝜇m.For NMOS devices a similar relationship can be seen where the channelresistance is 49Ω for a width of 500𝜇mand 8.1Ω for a device width of 5000𝜇m.The current density of the devices drop from 115𝜇𝐴/𝜇𝑚 for an NMOSdevice with a width of 500𝜇mto less than 80𝜇𝐴/𝜇𝑚 for a 5000𝜇m wide device. For PMOSthis density drop is smaller where the drop is from 33𝜇𝐴/𝜇𝑚 to 27𝜇𝐴/𝜇𝑚. A study on theeffects of implantation energy and scattering layer thicknesses showed thatboth lower energies and thicker layers yield higher drain currents and lowerchannel resistance. A possible explanation for this is that a shift in thethreshold voltage increased the overdrive voltage and therefore the draincurrent. In the investigation of the effects of direct illumination on theelectrical characteristics of the device it was found that the thresholdvoltage increases for PMOS devices from -0.21V under no illumination to -0.06Vunder full spectrum illumination at 1000𝑊/𝑚2 and decreases for NMOSdevices from 0.06V under no illumination to -0.15V under full spectrumillumination at 1000𝑊/𝑚2. Furthermore the off stategate leakage current increases by factor 33 under illumination at 1000𝑊/𝑚2 for NMOS devices and bya factor of 107 for PMOS devices. The electron mobility of the NMOS transistorincreases with incident light, improving the drain current gate voltagerelationship. The channel resistance for the NMOS devices improved between5-13%, depending on the intensity of the illumination, while the channelresistance of the PMOS increases up to 2%.A similar effect for the hole mobilityof the PMOS was not observed. Similarly, the channel resistance of the NMOStransistor improved, possibly due to the shift in threshold voltage or improvedelectron mobility. This improvement in performance was not recognized for PMOStransistors, however. A flowchart has been proposed for a process in which aMOSFET is fabricated on the backside of an Interdigitated Back Contacted (IBC)solar cell while combining as many steps as possible from their respectiveflowcharts to reduce complexity and costs, possibly leading the best balancebetween MOSFET and IBC fabrication.