The nature of silicon PN junction impedance at high frequency

Abstract

A thorough understanding of the small-signal response of solar cells can reveal intrinsic device characteristics and pave the way for innovations. This study investigates the impedance of crystalline silicon PN junction devices using TCAD simulations, focusing on the impact of frequency, bias voltage, and the presence of a low–high (LH) junction. It is shown that the PN junction exhibits the behavior of a parallel resistor–capacitor circuit (RC-loop) with fixed element values at low frequencies, but undergoes relaxation in both resistance R_j and capacitance C_j as frequency increases. Moreover, it is revealed that the addition of a LH junction impacts the impedance by altering R_j, C_j, and the series resistance R_s. Finally, while various publications on solar-cell impedance model the LH junction using an RC-loop, the findings in this study indicate that such a model does not accurately represent the underlying physics. Instead, this approach is likely compensating for the frequency-dependent behavior of R_j and C_j.