With the emerging wide bandgap (WBG) semiconductor development, the increasing power density and efficiency of power electronic converters may cause more switching oscillation, electromagnetic interference noise, and additional power loss, further increasing the probability of device failure. Therefore, determining and quantifying the failure of a metal-oxide-semiconductor-field-effect transistor (MOSFET), which assembled using WBG semiconductor in some applications, is crucial to improving the reliability of a power converter. This study proposes a novel failure quantitative assessment approach based on MOSFET parasitic parameters. According to the two-port network theory, MOSFET is equivalent to some second-order RLC circuits composed of independent inductances, capacitances, and resistances in series. Then, the frequency-domain impedance associated with the physical failure of MOSFET is identified through frequency domain reflectometry. Accelerated aging and bond wires cut-off experiments are employed to obtain various quality states of the MOSFET device. Result shows that the MOSFET quality level and its number of bond wire lift-offs can be quantified effectively. Drain-to-source on-resistance (R_DS(on)) that normally represents the MOSFET quality shows a positive linear function relationship on drain-to-source parasitic resistance (R_D + R_S) during the quality degradation proceeding. This finding matches with the correlation established between R_{DS (on)} and R_D + R_S in theory. Meanwhile, source parasitic inductance (L_S) increases with the severity of bond wires faults, and even the slight fault shows a high sensitivity. The proposed approach would be an effective quality screening technology for power semiconductor devices without power on treatment, which can effectively avoid the impact of junction temperature and test conditions (current and voltage) on test results, and does not need to design additional test circuits. The test frequency range we used in this approach was 10–300 MHz, which to some extent is suitable for providing an on-line quality monitoring technology for high-frequency WBG power devices manufacturing.

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For light-emitting diode (LED) package, interface delamination is a key factor that triggers reliability issues. When the delamination occurs in the thermal path of the die attach (DA) layer, the heat transfer capacity will be blocked and the junction temperature of the device will increase, which will affect various other failure mechanisms and ultimately reduces the life of the LED package. In this paper, the finite element method is used and based on entropy generation analysis. Interfacial delamination is prefabricated to the upper and lower interfaces of a model. The effects of cracks simultaneously appearing at different positions and lengths of the upper and lower interfaces on heat transfer are compared. Based on the simultaneous results, in the same position of the DA layer, the entropy generation value of delamination is larger than that without delamination, and the entropy generation value of delamination in the same position of the upper and lower interfaces is greater than that of not located in the same position. The larger the entropy generation value, the worse the heat transfer performance. And cracks appearing at the edge of the upper and lower interfaces have greater damage on heat conduction than the middle position. In addition, as the delamination length simultaneously increases at the upper and lower interfaces, the heat transfer performance becomes worse.@en

Silicon carbide (SiC) is a third-generation semiconductor material with many advantages, such as high thermal conductivity, high critical breakdown voltage, and high saturated electron drift velocity, which can increase the operating frequency of the power conversion system to more than 100kHz. In the high-frequency, the parasitic effect will significantly reduce the switching speed of the power devices, increase power consumption and influence the uniformity of current distribution. In this paper, we established the calculation nodes of each part of the SiC-MOSFET Half-bridge power module and used ANSYS Q3D software to extract the parasitic parameters. Die-Die, Die-DBC-1, Die-DBC-2 and hybrid interconnect package structures were designed to optimize the parasitic inductance. Simulation results indicated that the chip-DBC-1 structure can reduce the parasitic inductance about 30% compared with Chip-Chip structure and effectively control the uniformity of current density on two parallel diode chips (ΔLdiode <0.1%). In the meantime, an 3D model of partial bond wires broken were designed to get further insight into the variation of parasitic inductances. The correlation mechanism between the partial bond wires broken and inductance change of the D-S terminals current path was studied. The results showed that as the number of broken bond wires increases, the inductance of D-S terminals current path was increased gradually. Finally, by using two-port S-parameters measurement method to extract the inductances of the discrete power device, the experimental results indicated that when one or two bond wires were broken, the inductance of D-S terminals current path increased by 4.69% and 15.69%, respectively. Overview, a risk evaluation method for SiC power devices based on the variation of the parasitic parameters of the bond wire was established.@en