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AJ van de Goor Ph D

22 records found

Transient faults in DRAMs: concept, analysis and impact on tests

Facilitating automatic test pattern generators using test point insertion

Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs

Tests for resistive and capacitive defects in address decoders

Impact of memory cell array bridges on the faulty behavior in embedded

Test point insertion for compact test sets

March tests for realistic faults in two-port memories

Testing address decoder faults in two-port memories: fault models, test, consequences of port restrictions, and test strategy

Functional memory faults: a formal notation and a taxonomy

Industrial evaluation of DRAM SIMM tests

An experimental analysis of spot defects in SRAMs: realistic fault models and test

Defining SRAM resistive defects and their simulation stimuli

March tests for word-oriented two-port memories

Industrial evaluation of DRAM tests

Port interference faults in two-port memories

Illegal state space identification for sequential circuit test generation

The challenge of supplying quality DIMMs to the PC market
Journal article (1999) - AJ van de Goor Ph D (author)

Designing a memory module tester

Logical fault detection of CMOS SRAM ICs based on write quiescent supply current

Testability of the Philips 80C51 micro-controller