Av

AJ van de Goor Ph D

22 records found

Facilitating automatic test pattern generators using test point insertion

Transient faults in DRAMs: concept, analysis and impact on tests

Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs

Tests for resistive and capacitive defects in address decoders

March tests for realistic faults in two-port memories

Functional memory faults: a formal notation and a taxonomy

Test point insertion for compact test sets

Testing address decoder faults in two-port memories: fault models, test, consequences of port restrictions, and test strategy

An experimental analysis of spot defects in SRAMs: realistic fault models and test

Impact of memory cell array bridges on the faulty behavior in embedded

Industrial evaluation of DRAM SIMM tests

Designing a memory module tester

March tests for word-oriented two-port memories

Industrial evaluation of DRAM tests

Port interference faults in two-port memories

The challenge of supplying quality DIMMs to the PC market
Journal article (1999) - AJ van de Goor Ph D (author)

Fault (in)dependent cost estimates and conflict-directed backtracking to guide sequential circuit test generation

Testability of the Philips 80C51 micro-controller

Illegal state space identification for sequential circuit test generation

Industrial evaluation of stress combinations for march tests applied to SRAMs