The supply current of plastic encapsulated microelectronic devices in the presence of a high potential source can increase abnormally due to parasitic gate leakage. According to reliability qualification standards, stress during a parasitic gate leakage test is applied by a corona discharge at a thin tungsten needle placed a few centimeters above the devices under test. The gate leakage sensitivity factor obtained from this test lacks any physical basis and is therefore not believed to be useful. Here we show that this sensitivity factor can be replaced by a physical model for charge transport through the encapsulation material. The model is used to explain why devices encapsulated by a molding compound with a low volume resistivity of 6x10(11) Ohm.cm, at high temperature, 150º C, are more prone to fail the test on an increased current, compared to devices encapsulated by a compound having a high resistivity of 4x10(13) Ohm.cm at the same temperature. Furthermore, we discuss an alternative test setup where the potential difference between two parallel electrodes sandwiching the devices is used as the source of stress. It is suggested in literature that this setup yields identical results as the current setup. However, using both setups on the same product did not result in an equal outcome, which indicates that both tests do not trigger the same failure mechanism to the same extent.@en