Alternatives to CMOS logic circuit implementations are under research for future scaled electronics. Memristor crossbar-based logic circuit is one of the promising candidates to at least partially replace CMOS technology, which is facing many challenges such as reduced scalability, reliability, and performance gain. Memristor crossbar offers many advantages including scalability, high integration density, nonvolatility, etc. The state-of-the-art for memristor crossbar logic circuit design can only implement simple and small circuits. This paper proposes a mapping methodology of large Boolean logic circuits on memristor crossbar. Appropriate place-and-route schemes, to efficiently map the circuits on the crossbar, as well as several optimization schemes are also proposed. To illustrate the potential of the methodology, a multibit adder and other nine more complex benchmarks are studied; the delay, area and power consumption induced by both crossbar and its CMOS control part are evaluated.@en

Memristive device or memristor is a promising emerging technology due to its good scalability, near-zero standby power consumption, high integration density, and CMOS fabrication compatibility. Several potential applications based on memristor technology have been proposed, such as non-volatile memories, neuromorphic systems, and resistive computing. However, research on resistive computing is still in its infancy phase. Therefore, it faces challenges with respect to the development of the device technology, logic design styles, computer architectures, compilers and applications. This thesis focuses on the logic design (including primitive logic gates, interconnect, circuit, and synthesis flow) and a novel non-Von Neumann architecture.@en

CMOS technology and its continuous scaling have made electronics and computers accessible and affordable for almost everyone on the globe; in addition, they have enabled the solutions of a wide range of societal problems and applications. Today, however, both the technology and the computer architectures are facing severe challenges/walls making them incapable of providing the demanded computing power with tight constraints. This motivates the need for the exploration of novel architectures based on new device technologies; not only to sustain the financial benefit of technology scaling, but also to develop solutions for extremely demanding emerging applications. This paper presents two computation-in-memory based accelerators making use of emerging memristive devices; they are Memristive Vector Processor and RRAM Automata Processor. The preliminary results of these two accelerators show significant improvement in terms of latency, energy and area as compared to today's architectures and design.@en

CMOS technology and its sustainable scaling have been the enablers for the design and manufacturing of computer architectures that have been fuelling a wider range of applications. Today, however, both the technology and the computer architectures are suffering from serious challenges/ walls making them incapable to deliver the right computing power at pre-defined constraints. This motivates the need of exploring new architectures and new technologies; not only to maintain the economic benefit of scaling, but also to enable the solutions of emerging computer power and data storage hungry applications such as big-data and data-intensive applications. This paper discusses the emerging memristor device as complementary (or alternative) to CMOS device and shows how this device can enable new ways of computing that will at least solve the challenges of today's architectures for some applications. The paper shows not only the potential of memristor devices in enabling new memory technologies and new logic design styles, but also their potential in enabling memory intensive architectures as well as neuromorphic computing due to their unique properties such as the tight integration with CMOS and the ability to learn and adapt.@en

As today's CMOS technology is scaling down to its physical limits, it suffers from major challenges such as increased leakage power and reduced reliability. Novel technologies, such as memristors, nanotube, and graphene transistors, are under research as alternatives. Among these technologies, memristor is a promising candidate due to its great scalability, high integration density and near-zero standby power. However, memristor-based logic circuits are facing robustness challenges mainly due to improper values of design parameters (e.g., OFF/ON ratio, control voltages). Moreover, process variation, sneak path currents and parasitic resistance of nanowires also impact the robustness. To realize a robust design, this paper formulates proper constraints for design parameters to guarantee correct functionality of logic gates (e.g., AND). Our proposal is verified with SPICE simulations while taking both device variation and parasitic effects into account. It is observed that the errors due to analytical parameter constraints are typically within 4.5% as compared to simulations.@en

Memristor technology is a promising alternative to CMOS due to its high integration density, near-zero standby power, and ability to implement novel resistive computing. One of the major limitations of these architectures is the limited endurance of memristor devices, especially when a logic gate requires multiple steps/switching to execute the logic operations. To alleviate the endurance requirement and improve the performance, we present a novel logic design style, called scouting logic that executes any logic gate by only reading the memristor devices and without changing their states. Hence, no impact on the memristors' endurance. The proposed design is implemented using two styles (current and voltage based). To illustrate the performance of scouting logic based designs, the area, delay, and power consumption are analyzed and compared with state-ofthe- art. The results show that scouting logic improves the delay and power consumption by at least a factor of 2.3, while having similar or less area overhead. Finally, we discuss the potential applications and challenges of scouting logic.@en

Today's computing systems suffer from a memory/communication bottleneck, resulting in high energy consumption and saturated performance. This makes them inefficient in solving data-intensive applications at reasonable cost. Computation-In-Memory (CIM) architecture, based on the integration of storage and computation in the same physical location using non-volatile memristor crossbar technology, offers a potential solution to the memory bottleneck. An efficient interconnect network is essential to maximize CIM's architectural performance. This paper presents three interconnect network schemes for CIM architecture; these are (1) CMOS-based, (2) memristor-based and (3) hybrid cmos/memristor interconnect network scheme. To illustrate the feasibility of such schemes, a CIM parallel adder is used as a case study. The results show that the hybrid interconnect network scheme achieves a higher performance in comparison with the CMOS-based and memristor-based interconnect scheme in terms of delay, energy and area.@en

Today's computer architectures suffer from many challenges, such as the near end of CMOS downscaling, the memory/communication bottleneck, the power wall, and the programming complexity. As a consequence, these architectures become inefficient in solving big data problems or general data intensive applications. Computation-in-memory (CIM) is a novel architecture that tries to solve/alleviate the impact of these challenges using the same device (i.e., the memristor) to implement the processor and memory in the same physical crossbar. In order to analyze its feasibility in depth, this paper proposes two memristor implementations of a data intensive arithmetic application (i.e., parallel addition). To the best of our knowledge, this is the first paper that considers the cost of the entire architecture including both crossbar and its CMOS controller. The results show that CIM architecture in general and the CIM parallel adder in particular have a high scalability. CIM parallel adder achieves at least two orders of magnitude improvement in energy and area in comparison with a multicore-based parallel adder. Moreover, due to a wide variety of memristor design methods (such as Boolean logic), tradeoffs can be made between the area, delay, and energy consumption.@en

In this paper, we briefly discuss a new proposed architecture, Computation-In-Memory (CIM) architecture, that targets specifically data-intensive applications. The architecture consists of the interwoven placement of computing and storage units, which are physically tightly integrated together inside a non-volatile memristor crossbar. The architecture has the potential of improving the energy-delay product, computing efficiency and performance per area by at least two orders of magnitude with respect to conventional CMOS architectures.@en

Memristor crossbar is a promising technology for future VLSI circuits due to its scalability, non-volatility, high integration density, etc. However, sneak path currents in the crossbar pose major robustness challenges. One proposed solution is applying half-select voltages to floating nanowires (which are not involved in logic operations). This paper analyzes the sneak path issue after applying half-select voltages, and then uses this analysis to derive a set of realization parameter constraints for robustness. In addition, the constraints are used to estimate maximal crossbar size of logic circuits. As a case study, a one-bit full adder is implemented and verified with SPICE simulations; the results show that the proposed approach accurately predicts the impact of sneak path currents with a maximal error of 0.06V.@en

Many emerging technologies are under investigation to realize alternatives for future scalable electronics. Memristor is one of the most promising candidates due to memrsitor’s non-volatility, high integration density, near-zero standby power consumption, etc. Memristors have been recently utilized in non-volatile memory, neuromorphic system, resistive computing architecture, and FPGA to name but a few. An FPGA typicallyconsists of configurable logic blocks (CLBs), programmableinterconnects, configuration, and block memories. Most of therecent work done was focused on using memristor to build FPGA interconnects and memories. This paper proposes two novel FPGA implementations that utilize memristor-based CLBs and their corresponding automatic design flow. To illustrate the potential of the proposed implementations, they are benchmarked using Toronto 20, and compared with the state-of-the-art in terms of area and delay. The experimental results show that both the area (up to 4.24x) and delay (up to 1.46x) of the novel FPGAs
are very promising.@en

Emerging technologies are under research as alternatives for next-generation VLSI circuits. One of the promising candidates is memristor due to its scalability, high integration density, non-volatility, etc. Different design styles of memristor-based logic circuits have been proposed. This paper first overviews these design styles and compares them using several criteria. Subsequently, it selects a promising candidate to explore its potential logic gate space. Thereafter, it derives control voltage constraints used to ensure correct logic gate functionality. The newly obtained logic gates are verified by SPICE simulations, and finally the performance of the memristor gates are compared with CMOS gates. The results show that the memristor gates, with reasonable technology improvements, are comparable to CMOS gates or even outperform them.@en

Memristors are emerging devices with huge potentials. It has been shown that they can be used not only to design non-volatile memories, but also logic circuits. In the latter, memristor devices are stacked on a CMOS circuit which generates the required control signals needed by the memristors to perform the required functionality. This paper sets a step towards automating this process; it proposes a generic synthesis framework to map logic circuits on memristor crossbar. The framework takes HDL descriptions as input and generates both its memristor circuitry and its associated CMOS control. The framework consists of three phases: (i) netlist generation, (ii) partition and mapping, and (iii) placement and routing. To illustrate the framework, a combinational and a sequential circuit are investigated. The results are validated using HSPICE simulations.@en

One of the most critical challenges for today's and future data-intensive and big-data problems is data storage and analysis. This paper first highlights some challenges of the new born Big Data paradigm and shows that the increase of the data size has already surpassed the capabilities of today's computation architectures suffering from the limited bandwidth, programmability overhead, energy inefficiency, and limited scalability. Thereafter, the paper introduces a new memristor-based architecture for data-intensive applications. The potential of such an architecture in solving data-intensive problems is illustrated by showing its capability to increase the computation efficiency, solving the communication bottleneck, reducing the leakage currents, etc. Finally, the paper discusses why memristor technology is very suitable for the realization of such an architecture; using memristors to implement dual functions (storage and logic) is illustrated.@en