Performance Enhancement with a Capacitor-Scaling Design for SSHC Piezoelectric Energy Harvesting Interfaces

Abstract

Piezoelectric energy harvesting (PEH) has attracted much attention as an approach to exploit ambient vibrational energy to power self-sustained devices. Among the proposed interface circuits for PEH, Synchronized Switch Harvesting on Capacitor (SSHC) rectifier distinguishes itself since it achieves high power efficiency while requires no inductor. The power SSHC can extract is a function of the voltage flip efficiency. In previous studies the flip efficiency is given only under particular condition, which limits the analysis and design of SSHC circuits. This paper presents the derivation of a generic flip efficiency expression. From the result, a novel capacitor-scaling design is proposed which can reduce the total switched capacitance by up to 50% while achieving the same performance (or to enhance performance while maintaining the total capacitance). This is particularly preferred for a fully integrated design and can validated by simulations implemented in a 0.18 m. CMOS BCD technology.