A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology

Conference paper (2022)

Authors

Zhongkai Wang University of California
Minsoo Choi Samsung Semiconductor
Paul Kwon University of California
Kyoungtae Lee University of California
Bozhi Yin University of California
Zhaokai Liu University of California
Kwanseo Park University of California
Ayan Biswas University of California
S. Du Electronic Instrumentation - EEMCS
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Research Group
Electronic Instrumentation (EEMCS) (TU Delft)
Copyright: © 2022 Zhongkai Wang, Minsoo Choi, Paul Kwon, Kyoungtae Lee, Bozhi Yin, Zhaokai Liu, Kwanseo Park, Ayan Biswas, S. Du, More Authors
DOI: https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830237
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Published Date

2022

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Research Group

Electronic Instrumentation

Abstract

This paper presents a complete 200Gb/s PAM-4 transmitter (TX) in 28nm CMOS technology. The transmitter features a hybrid sub-sampling PLL (SSPLL) with a delta-sigma (?S) modulator, clock distribution network with flexible timing control, and data path with a hybrid 5-tap Feed-Forward Equalizer (FFE) and T-coil for bandwidth extension. The prototype chip achieves 4.69 pJ/bit efficiency, 54mV eye height, 0.27UI eye width, and 97% RLM under -6dB channel loss at 50GHz.

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