A Ring-Oscillator Sub-Sampling PLL With Hybrid Loop Using Generator-Based Design Flow

Conference paper (2022)

Authors

Zhongkai Wang University of California

Minsoo Choi Samsung Semiconductor

John Wright University of California

Kyoungtae Lee University of California

Zhaokai Liu University of California

Bozhi Yin University of California

Jaeduk Han Hanyang University

S. Du Electronic Instrumentation -

Elad Alon University of California

Research Group

Electronic Instrumentation () (TU Delft)

DOI: https://doi.org/10.1109/ISCAS48785.2022.9937615

Hybrid PLL Ring oscillator Sub-sampling PLL generator

To reference this document use:

http://resolver.tudelft.nl/uuid:06f907ea-7cbb-46bb-863f-87229532e41c

More Info

expand_more

Published Date

2022

Language

English

Reuse Rights

Other than for strictly personal use, it is not permitted to download, forward or distribute the text or part of it, without the consent of the author(s) and/or copyright holder(s), unless the work is under an open content license such as Creative Commons.

Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Research Group

Electronic Instrumentation

Abstract

We present a ring-oscillator-based sub-sampling phase-locked loop (PLL) using a generator-based design flow. A hybrid loop with a delta-sigma ($\Delta \Sigma$) modulator is applied to reduce the loop filter (LF) area and the control ripple. The generator automatically produces the ring oscillator and PLL to meet the provided specifications. The 10-GHz PLL instance implemented in 28-nm planar process achieves RMS jitter of}299.5 fs and power of 9.9 mW from a 1-V supply.

Files

A_Ring_Oscillator_Sub_Sampling... (pdf)

(pdf | 2.26 Mb)

- Embargo expired in 01-07-2023