With the rising demand for high-bandwidth, high-resolution current sensors, commonly used Hall-effect devices fall short due to their relatively high wide-band noise. The coil-Hall hybrid architecture addresses this issue by combining the Hall plate with a pick-up coil, known for its high SNR at high frequencies. This CMOS-compatible architecture achieves excellent noise and bandwidth performance while maintaining the ability to sense DC signals. However, this performance comes at the cost of increased complexity in combining, calibrating, and stabilizing the two distinct signal paths. This thesis thoroughly investigates the various challenges and trade-offs associated with this architecture and provides a comprehensive overview of potential system solutions. Additionally, the insights gained were used to design a prototype chip for SystematIC Design B.V. Seeking to reduce complexity, this led to the invention of a new system architecture. This new architecture effectively overcomes several challenging trade-offs that have hindered existing designs until now and is considered a promising approach for achieving even better performance in the future.

Class D amplifiers find widespread application in audio devices for driving load speakers, primarily due to their remarkable efficiency. Nonetheless, this enhanced efficiency often comes at the expense of reduced linearity. Hence, techniques for reducing Total Harmonic Distortion (THD) are important in the context of class D amplifiers.

The analysis of the distortion mechanisms is first presented. Specifically, emphasis is placed on the distortion generated within the power stage, encompassing aspects such as deadtime distortion and rising and falling time distortion. Both of them are found to be related to the input signal. Subsequently, the compensation technique is applied to the conventional class D amplifier to reproduce and cancel the error. The idea of the compensation approach involves modifying the amplitude of the triangular waveform based on the input signal. A 12 dB THD improvement is achieved in the concept verification section, which is conducted in LTspice.

The negative feedback serves as another technique to achieve THD reduction. A straightforward two-step design methodology is presented to avoid design iterations in the concept design phase. The phantom zero technique is applied when doing the frequency compensation of the feedback loop. The validation of the concept is performed through the use of SLICAP, while the circuit implementation and simulations are carried out within Cadence. Remarkably, this technique results in an impressive -111.8 dB THD reduction, achieved when the output power equals 1 W.

This report presents a bandgap reference voltage source that achieves 5-sigma Inaccuracy of ±0.5% from -40C to 150C under 16FFC process. This is the first time 16nm techniques are used in automotive products and the first time trying to realize analog circuits in such a process for in-vehicle network purposes. The report points to good behavior with only a small area and considerable power. It also proves that applying chopping to the circuit does not increase the area.

This thesis describes the design of a CMOS magnetic field sensor system for measuring electronic currents. A hybrid system, using Hall plates and a pick-up loop is chosen to obtain improved performance compared to conventional Hall based magnetic field sensors. The pick up loop enables to reduce the current consumption and increases the bandwidth of the system. The design of the pick-up loop and readout amplifier are described in detail. Simulation results of the pick-up loop signal path offer a factor 10 increase in bandwidth using 24% less current compared to a system consisting of two Hall plate channels.

This thesis discusses the basic architecture, design details, circuit implementation, and measurements of a digital class D current driver.
The driver contains two main parts: a digital control loop and analog circuits.
Parts of the important part in the digital control loop contain noise shaper, plant compensator, and cable capacitance compensator. The noise shaper has two core functions: 1. It seeks to minimize the difference between the process variable and the set point. 2. It shapes the noise that is generated in the forward loop. The plant compensator is used to compensate for the output filter, the load, and the cable. The cable capacitance compensation is a measure-based technique to generate a negative output capacitance to compensate for the cable capacitance. The analog circuits consist of a full bridge, data acquisition circuits, and floating supplies.
Multiple simulation models have been made in Matlab. According to the simulation results, the amplifier shows its flexibility and performance to handle a large range of inductive loads.
A prototype has been implemented. The measurement results show that most of the hardware performance is as intended. Due to the time limitation, the whole amplifier is not tested.

The need to understand how the brain works has sparked interest in electrode arrays to record neural signals. Intracellular recordings with nanoelectrodes that penetrate the cell allow better signal quality and additional functions such as voltage clamping to set the neuron's transmembrane voltage. The voltage clamp aims to facilitate the independent study of the ionic channel contributions to the overall neuron's transmembrane current for applications such as drug screening. This thesis aims to design a voltage clamp with CMOS technology to integrate into an intracellular neural interface system. The circuit, a trans-impedance amplifier, needs to be low-noise, small, and have wide clamping and output voltage ranges. The amplifier's design follows a structured methodology and uses symbolic analysis with the software SLiCAP and simplified EKV models aiming for easier readjustments and transparency for other researchers. The controller is an Operational Amplifier with a differential pair input-stage, an unbalanced common-source output-stage, and frequency compensation. The feedback network is a pseudo-resistor due to the enormous gains required to record the currents in the electrode of about 100 pA - 1 nA. The final simulations estimate a trans-impedance gain from the electrode to the load range of [2 M,1 G] V/A, a clamping voltage range of [0.90, 3.16] V, an output voltage range of [0.50, 3.16] V, and an output-referred noise between 0.095 and 0.41 mV_rms depending on the gain. The power usage is 49.1 uW/pixel and the area 0.0092 mm²/pixel. Post-layout simulations show stability degradation due to the influence of parasitics in the pseudo-resistor.

The objective of the project is to design a system which can control the temperature of a va-porizing liquid microthruster (VLM). The liquid in a VLM is heated using a heater resistor.This resistor will be used to both heat the liquid and measure the temperature.In this thesis the subsystem responsible for the measurements and the conversion of the mea-sured signals to the digital domain will be discussed. We propose a method where short measure-ment current pulses of a fixed amplitude are applied to the heater resistor. As an optimization,these pulses are omitted when a certain current threshold has been met.Results show that the system can measure temperature with±1◦C accuracy, however more fullsystem measurements are required to ensure functionality as a whole.