This thesis details the theoretical background and development process of a classification model for electroencephalogram-based (EEG) motor imagery (MI) signals, to be used in a brain-computer interface (BCI) system. This project was undertaken in order to demonstrate the possibility of distinguishing MI-EEG signals acquired using the g.tec Unicorn Hybrid Black EEG measurement cap. The classification model devised in this thesis is a hybrid deep neural network model, which combines a convolutional neural network (CNN) and long short-term memory (LSTM) recurrent neural network (RNN) in parallel, closing with a fully-connected (FC) layer. Much experimentation and research was needed to create this model, and this is extensively discussed within the thesis. The classification model produced for this thesis is one part of a complete end-to-end BCI system, which also entails a measurement and data processing procedure, and the development of a graphical user interface which provides visual feedback to the user.

On publicly available datasets, the classification model produced promising performance, achieving 55% on the BCI Competition IV-2a (4 class) dataset and 78% on the BCI IV-2a (2 class) dataset. The model has not yet been tested on self-collected data.

The main goal of this project is to utilize a commercially available OpenBCI Ultracortex IV for the measurement of Electroencephalogram(EEG) signals. A pipeline consisting of preprocessing, classification and extraction is employed to transform the motor execution EEG signal into a singular Left or Right output. This output is then further displayed on an Interface that offers the option to either calibrate or play a simple game.

The Ultracortex and relevant software were used to determine the sensor layout, with the placement of the sensors focused on areas which exhibited high cortical activity during motor execution. Experiments were strategically designed to optimize our chance of successful readings and OpenVIBE was used in conjecture with preprocessing filters to save the raw and filtered data which was further sent to the Machine Learning group.

The collected data was analyzed through Spectrograms, Power Spectral Density(PSD) and Event-Related Desynchronization/Synchronization(ERDS) plots. The analysis aimed to confirm whether the desired activity occurred and whether the observed patterns resemble those documented in other research papers.

The data from the headset is live-streamed to the interface via Lab Streaming Layer(LSL) where it undergoes further filtering before being sent to the Machine learning group. This process was done through python libraries which then allowed for efficient and effective communication between the other groups.

As technology nodes continue to shrink, more challenges arise in the field of Design for Testability (DfT). Sequential Integrated Circuits (IC) with asynchronous (re)set flip-flops are notorious for producing unwanted reset behaviour during scan-test. Typically the scan flip-flops are restricted to a non-reset state while the shift operation is performed. This can be achieved by inserting an independent test signal in parallel with each local reset port. This ensures that the scan flip-flops are loaded with the correct input data during the shift cycle. However, before the capture cycle is initiated, this test signal must be released as it prohibits the reset logic from being tested with stuck-at-faults. When there are multiple cascading resets present in the design this release can cause glitches to occur. Since the reset ports operate asynchronously, these glitches can also trigger a scan flip-flop to reset, thereby changing the input data. As a result, some chips may be tested with corrupted input data, leading to differences in scan patterns. Consequently, these ICs fail during manufacturing tests and are classified as faulty, leading to yield loss.


By adding DfT to the (re)set port of each flip-flop these glitches can be prevented at the cost of additional hardware. This thesis establishes the conditions that lead to the occurrence of asynchronous (re)set glitches during scan-test. A design rule-based algorithm is proposed that can accurately identify glitchy structures for circuits without reconvergence. As an extension, a simulation-based algorithm is presented that can further classify which (re)set flip-flops can cause a glitch. These algorithms have been tested on two case studies where glitches have been observed. After deploying these algorithms 33% and 71% of the total number of (re)set flip-flops were identified as glitch-free. By only adding additional DfT to these flip-flops the overhead is significantly reduced. This work addresses a significant challenge in minimizing the cost of robust asynchronous scan test.

In 2022, there were over 26 million electric automobiles on the road, a 60% increase with regard to 2021 and more than 5 times the stock in 2018. As automobiles become more electric and systems get increasingly complex, the safety requirements get more stringent. In 2011, the International Organization for Standardization (ISO) established ISO26262 to provide guidance to the semiconductor industry on the development process of safety essential ICs for automotive applications.

When evaluating the safety of a system parallel to the normal functional operation, traditional Design-for-Test (DFT) techniques such as scan chain, Built-In Self-Test (BIST), Joint Test Action Group (JTAG), and boundary scan are no longer viable options for two fundamental reasons. Firstly, safety assessment in the context of automotive applications necessitates evaluation at an application level, going beyond the capabilities of these techniques, which are primarily designed for structural and functional testing. Secondly, during safety checks, it is imperative that the normal operation of the integrated circuit (IC) remains uninterrupted, as the chip is often deployed in critical, real-time systems. These traditional DFT methods, while effective during the IC manufacture and production before they are released in the market, fall short of addressing the dynamic and application-specific safety concerns that arise during the operational lifecycle of safety-critical systems in sectors like automotive engineering.

To address these challenges, fault injection has emerged as the necessary step for safety assessment. ISO26262 explicitly recognizes fault injection as one of the most popular techniques for evaluating a system's safety and determining its Automotive Safety Integrity Level (ASIL). The safety metrics are required for certification of a product with ASIL. Fault injection allows for the creation of realistic fault scenarios and the assessment of how the system responds to these faults during normal operation, aligning more closely with the dynamic and application-specific nature of safety-critical systems in fields of automotive engineering.

Currently, many EDA companies provide Failure Mode Effects and Diagnostic Analysis (FMEDA) platforms for IC safety evaluations. However, these tools are time-consuming and resource-intensive. Additionally, as IC designs become more intricate, there is a reliance on fault reduction techniques such as statistical sampling, which entails simulating only a mere 5% of the overall fault space. Thus, an FPGA-based fault emulation system emerges as a promising approach to expedite this process.

The novelty of this work was in designing a dedicated platform tailored for the evaluation of safety-critical systems for automotive applications such as Battery Management Systems (BMS). This platform can execute the safety sequences on the system to evaluate the safety mechanisms implemented in the design in the presence of random faults assuming the chip is in use in the car. Moreover, the fault emulation activity provides the evidence necessary for the certification of products with ASIL level. Furthermore, performing this activity during the development stage helps in designing the ICs with the highest level of safety. The proposed FPGA-based fault emulation system efficiently overcomes three key challenges: it decreases execution time dramatically provides a speed-up of 296x compared to the simulation method, optimizes resource utilization, eliminates the tool license cost, and removes the requirement for considerable fault space reduction. This platform can emulate a large fault population of up to one million faults in less than three hours.