The quantum bits (qubits) at the core of any quantum computers are so fragile that quantum error correction(QEC) schemes are needed to increase their robustness and enable fault-tolerant quantum algorithms. The surface code is one of the most popular QEC schemes, but it requires the availability of an efficient decoder. While neural networks have been shown to be well suited to this task, only software implementations have been studied in prior work. These have shown that neural network decoders can be on par or better than other decoding algorithms, but lack the required speed when running as software. The aim of this thesis is to investigate the hardware implementation of the neural networks for the decoders of surface codes to achieve the required speed. Most electronic hardware employed in quantum computers today operates at room temperature and is connected by bulky wires to the qubits, which are placed in a cryogenic chamber for proper operation. Since any useful quantum computer will comprise thousands or even millions of qubits, this work proposes to also move the QEC hardware to cryogenic temperatures (4 K). However, because at these temperatures the cooling power of cryogenic refrigerators is limited, the hardware needs to be low power, while ensuring enough speed to keep the pace of the QEC. The exploration of this work sweeps multiple parameters of a feed-forward neural network to find what the influence is on the decoder performance and the delay, the power, and the area. The parameters that are swept are the number of hidden layers, their sizes, the type of transfer functions and the number of bits used in the quantization of the weights and outputs. The results show that using the configurations found in this work it is possible to meet the performance and timing constraints using cryo-CMOS on both an FPGA and in a 40-nm technology. Although there are still some limitations in this work, such as the scaling in the power consumption and decoding performance for larger distances, there are multiple proposed improvements, making this is a stepping stone towards a future scalable implementation of QEC.

Voltage references are one of the fundamental building blocks for designing any analog processing circuit. It serves as a reference for Analog to Digital Converters (ADCs), Digital to Analog Converters (DACs), power/voltage regulators and other measurement and control circuits. The performance of all these circuits cannot be better than the performance of the reference. Hence, it is very important that the voltage reference is very robust and performs reliably under process, supply, temperature or noise variations (PVT & N). Today, with the development of scalable quantum computing, there is a need for such a reference operating at cryogenic temperatures. Currently, the state of the art quantum circuits operates at ∼20 mK. To process and control the information flow, to and from these quantum processors, one requires an analog circuit to operate as close as possible to the quantum circuit, so as to make the full system scalable and more reliable since no line interconnect to room-temperature electronics would be required. As a step towards that idea, it is desired to push the operating temperature of the classical circuits as low as 4 K where enough cooling power is available without disturbing the operation of the quantum circuit. One of the basic blocks to be shifted to cryogenic temperatures is the voltage reference circuit. This thesis presents a systematic design of such a cryogenic voltage reference block, taking into account the device and circuit performance at 4 K. The targeted specifications are comparable to the references designed for standard industrial temperature range (233 K to 400 K). However, it is designed to work over an extremely wide temperature range (4 K to 400 K) to understand how far one can stretch the circuits designed with conventional CMOS. Two different variants of references are presented with the simulated performance of both over the industrial temperature range. A novel approach towards higher-order compensation is also presented which is expected to perform better than conventional CMOS reference over a wide range. To test their performance over the entire operating range (4 K to 400 K) and verify the designs, a tape-out is planned for October 2019.

High speed imagers find applications in many fields such as scientific and medical imaging, automotive applications, machine vision and much more. In this thesis, the design of a high speed, high dynamic range (HDR) CMOS sensor with electronic global shutter (GS) and flexible exposure control is presented. The sensor is designed in the 0.11μm CIS process, features 1k(H) x 1k(V) pixels and achieves frame rates greater that 10.000 fps.A review of the architecture of the sensor is given, along with functional illustrations for each comprising block. The quadrant-based approach is described, along with the selectable region-of-interest capability. The pixel design is a eleven-transistor (11T) pinned photodiode global shutter pixel, implementing HDR by means of two in-pixel capacitors. The design of the pipelined Sample & Hold, column gain and column-level Correlated Double Sampling (CDS) circuits are shown.

Quantum computers are able to deal with large problems, like molecular modelling, financial prediction and cryptography. A classical controller is used to control the qubits of the quantum computer. A proposed controller, operating at 4K, needs a clean voltage supply in order to function well. The long interconnects between the room temperature power supplies and the 4K classical controller are not loss-less and do have parasitic capacitance and inductance. Low drop-out (LDO) voltage regulators are able to clean this dirty supply voltage and produce a stable, regulated voltage. Therefore, a cryogenic 40nm CMOS LDO voltage is designed. This regulated is designed with room temperature models and optimized for operating at 4K. The specification are competitive to other LDO voltage regulators.

Quantum computers seem very promising in solving problems that are too large to be solved by classical computers that are available today. However, to generate reasonable amounts of computing power, many qubits will be required. Each of the qubits has to be individually controlled and needs to be kept at cryogenic temperatures. To allow for the scaling of the number of qubits, control electronics are being developed, that operate close to the qubits, at a temperature of 4 Kelvin. These control electronics require a voltage reference as well. In this thesis, several voltage references implemented in a commercial 40-nm CMOS process will be presented. The voltage references are designed for the temperature range from 4.2 K up to 400 K. As bipolar transistors are not suited for operation at cryogenic temperatures, the references are implemented using MOS devices. Architectures employing NMOS, PMOS and DTMOS as core device have been implemented.