Gate-defined quantum dots are a promising candidate system for realizing scalable, coupled qubit systems and serving as a fundamental building block for quantum computers. However, present-day quantum dot devices suffer from imperfections that must be accounted for, which hinders the characterization, tuning, and operation process. Moreover, with an increasing number of quantum dot qubits, the relevant parameter space grows sufficiently to make heuristic control infeasible. Thus, it is imperative that reliable and scalable autonomous tuning approaches are developed. This meeting report outlines current challenges in automating quantum dot device tuning and operation with a particular focus on datasets, benchmarking, and standardization. We also present insights and ideas put forward by the quantum dot community on how to overcome them. We aim to provide guidance and inspiration to researchers invested in automation efforts.@en

Spins in gate-defined silicon quantum dots are at the forefront of solid-state qubit research. We characterize top-gated devices fabricated from Si/SiGe heterostructures, demonstrating the formation of stable double and triple quantum dots with proximal charge-sensing dots. We also demonstrate fabrication of linear dot arrays with overlapping gate technology, thereby significantly increasing the density of control electrodes relative to our single-gate-layer devices.

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Quantum dot arrays are a versatile platform for the implementation of spin qubits, as high-bandwidth sensor dots can be integrated with single-, double-, and triple-dot qubits yielding fast and high-fidelity qubit readout. However, for undoped silicon devices, reflectometry off sensor ohmics suffers from the finite resistivity of the two-dimensional electron gas (2DEG), and alternative readout methods are limited to measuring qubit capacitance, rather than qubit charge. By coupling a surface-mount resonant circuit to the plunger gate of a high-impedance sensor, we realized a fast charge sensing technique that is compatible with resistive 2DEGs. We demonstrate this by acquiring at high speed charge stability diagrams of double- and triple-dot arrays in Si/SiGe heterostructures as well as pulsed-gate single-shot charge and spin readout with integration times as low as 2.4 μs.

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