The use of microelectronic components in mobile appliances is constantly increasing. Appliances like mobile phones, PDA's and navigation systems contain more and more functionality and smaller microelectronic components.@en

Low-Ag solder SnAgCu (SAC) is more suitable for improving the shock performance of solder joints as reported by many papers. However the properties of low-Ag solder, with different Cu contents, under service conditions are lacking. The forming mechanism of the intermetallic compound (IMC) and the relation with the joint strength need to be investigated. In this study, the effects of high-temperature storage (HTS) aging on the joint performance of low-Ag solders/UBM (Ni(P)-Au) are examined for wafer-level chip-scale packages (WLCSP). Three types of solder balls with different Cu content are considered. The interfacial morphology and microstructure of the solder joints are investigated by SEM, EDX and deep etching techniques. The high-speed cold bump pull (HSCBP) test is used to analyse the joint strength. Results indicate that HTS aging for solder balls containing different amounts of Cu results in joint strength decreases. Solder joints with a low-Cu percentage appear to have a higher aging resistance than a solder joint with a high-Cu percentage. Too much Cu in the solder results in both a large amount of voids and the Cu3Sn layer growing near the Cu6Sn5 layer in the interface after HTS aging, leading to reduced joint strength. The IMC in the interface of solder/Under-Bump Metallization (UBM) exhibits different morphologies and microstructures due to the solder balls with different amounts of Cu and the aging parameters. The microstructure and fracture mode of the IMC affect the pull strength of the joint. Moreover, Cu content within solder ball is a key reliability factor.@en

The use of microelectronic components in mobile appliances is constantly increasing. Appliances like mobile phones, PDA's and navigation systems contain more and more functionality and smaller microelectronic components. Dropping an appliance during its lifespan is very common and the product is required to survive this. The drop however generates significant forces and vibrations on the internal assembly of the product. The performance of a microelectronic component under drop conditions has thus become an important reliability parameter. Assessing the solder interconnect quality by means of drop impact testing, as standardized by e.g. JEDEC, during normal production requires considerable amounts of time and effort. Besides this, the repeatability of the drop impact test is low and introduces elaborate and time-consuming analysis of the results after testing. Already many researchers have investigated new test techniques capable of replacing the drop impact test, e.g. high-speed shear [1], pull [2] and bending. Among those tests is the High Speed Cold Bump Pull test (HSCBP or CBP). In the CBP test the solder bump is pulled in vertical direction from the die using a small pair of jaws. In this test, by varying the pull speed several different strain-rates can be applied to the solder bump. In our research a correlation between the drop impact test and cold bump pull test is investigated. This can be divided into three parts. First by investigating the cold bump pull test apparatus for uncontrolled parameters that might introduce a biass or spread in the results. Secondly by means of modeling the cold bump pull test to investigate solder bump deformation and solder bump loading during pull-off. Finally in a comparison the differences and similarities between the two tests are briefly discussed and some observations concerning the solder joint performance are presented. The correlation between the two tests is focused on a method capable of translating the loading conditions experienced in the drop impact test towards a cold bump pull test prescription. Several numerical simulations have been used to investigate the solder ball during deformation and destruction. The cold bump pull experiments are used to rule out as much variances as possible and improvements for the cold bump pull apparatus are proposed.@en

With the increased use of mobile phones, navigation systems, PDA's, laptops and portable gaming devices, the drop reliability of microelectronics has become an important parameter. Assessing the solder interconnect quality by means of drop impact testing, as standardized by e.g. JEDEC, during normal production requires considerable amounts of time and effort. Besides this, the repeatability of the drop impact test is low and introduces elaborate and time-consuming analysis of the results after testing. Already many researchers have investigated new test techniques capable of replacing the drop impact test, e.g. high-speed shear, pull and bending. Among those tests is the High Speed Cold Bump Pull test (HSCBP or CBP). In the CBP test the solder bump is pulled in vertical direction from the die using a smal pair of jaws. In this test, by varying the pull speed several different strain-rates can be applied to the solder bump. In our research a correlation between the drop impact test and cold bump pull test is investigated. This can be divided into three parts. First by investigating the cold bump pull test apparatus for uncontrolled parameters that might introduce a bias or spread in the results. Secondly by means of modeling the cold bump pull test to investigate solder bump deformation and solder bump loading during pull-off. Finally, the differences and simularities between the drop impact test and the cold bump pull test are briefly discussed and some observations concerning the solder joint performance are presented.@en