Machine learning on edge devices performs crucial identification or prediction tasks while limiting the amount of data that needs to be transmitted to more centralized computing nodes. However, strict area and energy requirements necessitate specialized hardware developed for the requirements of the device and model. This thesis is concerned with developing an area and energy arithmetic unit as part of the implementation of a stacked machine learning model in embedded automotive devices. The model in question was previously designed to perform lifetime prediction with the goal of improving the reliability of semiconductor devices used in various automotive applications.

This thesis aims to achieve area and energy efficiency by exploiting the commonalities in the arithmetic operations of several of the internal learners of the stacked machine learning model. The use of a weighted figure of merit, taking into account area, energy and delay, allow for simple comparisons of designs at any operation frequency and easy insight into the changes in the merit of designs if device requirements were to change. A sweep of the percentage of multiplications in the workload also gave insight into how design choices may change due to future redesigns of the stacked machine learning model.

It was found that the MAC, multiply, divide and accumulate operations of the internal learners can best be supported by one arithmetic unit containing a "Reduced Area" parallel multiplier (still taking up most of the area), a small, dedicated accumulator and invariant integer division using the multiplier. It was also found that the ability to reconfigure the multiplier for different levels of bit-precision does not yield performance improvement for the expected precision distribution.

The increased heat on an integrated circuit is a limiting factor for the performance and lifetime of a chip. The increased power density on chips resulted in increased heat and the formation of non-uniform hotspots. Earlier research has shown that the package design and layout of package components in flip-chip design can influence the thermal heat distribution on a chip. Especially the copper pillars play a role in the distribution of heat on a chip. These pillars can reduce the maximal temperature of a hotspot when placed correctly. Designing a pillarmap that adheres to manufacturing rules can be lengthy and complex. Therefore, pillarmaps are currently not optimised for thermal behaviour. The default strategy is to place them in a grid. This research aims to automatically optimise pillarmaps for thermal heat distribution with the use of artificial intelligence. Pillarmaps are optimised using the theoretical behaviour of heat in packages combined with Stochastic Hill Climbing and Squeaky Wheel Optimisation techniques. The layouts are automatically re-simulated in a finite elements simulation tool when needed. The optimisation strategies are tested on experimental setups with single and dual hotspots. The optimisation strategies are also evaluated on an actual product, but limitations on pillar placement reduced the effect of the optimisation techniques. Also, the influence of different pillar diameters on an optimisation strategy is discussed. The optimisation techniques can reduce hotspots and improve the heat distribution in a scenario with multiple hotspots. The success of the optimisation techniques is subject to the amount of freedom they have to change pillar locations and where the hotspots are on the chip.

THERMAL management is a very crucial step to ensure the reliability of Integrated Circuits (IC)s. The increase in power density has resulted in the formation of multiple, high-intensity, and non-uniform hotspots. This has not only affected the lifetime but also the performance of several devices. Optimization of the package design and layout are the methods investigated to solve this problem. In flip-chip packaging, each IC product varies with respect to power densities, die area, pin-count, laminate and PCB layers, etc. It is therefore important in understanding how the arrangement and geometry of each layer (in particular the interconnect layer) impacts the overall thermal management.