This work describes accurate methods for the characterization of sub-terahertz (sub-THz) devices and pad de-embedding procedures. The extraction of the intrinsic DUT is enabled by generating a precise pad model using two-tier calibration approaches. Moreover, the proposed approaches offer a solution to the designers to preserve precious silicon area by presenting a simplified and potentially parameterizable pad model. Employing two different thru-reflect-line (TRL) calibration kits (calKits) together with the DUT on the same die, this research validates the proposed calibration strategies. This paper uses as DUT at J-band, i.e. a Marchand balun, fabricated using IHP SiGe BiCMOS technology with an aluminum back-end-of-line (BEOL), alongside the mentioned calKits. The goal of the paper is to assess the performance of the DUT and validate two de-embedding methods. Moreover, the pad model offers a way for accurate DUT characterization saving silicon area for future optimized designs.@en

In this paper, we present a low-noise, high-gain readout hardware to be used in conjunction with (sub)mm-wave zero bias detectors, to enable high sensitivity (i.e., ∼-50dBm) and fast (i.e., below a second at -50 dBm) power detection.

The developed hardware employs a cascade of two (COTS) programmable gain amplifier (PGA), capable of reaching up to 90 dB gain (volt to volt), each providing an input referred noise level of 16 nV/√Hz. The signal is then digitized on the same board via a 500 kHz 12bit ADC, providing an SNR of 74 dB. The digitized signal is then readout via an ST microcontroller and transferred to the operator PC via a USB interface. The sensitive bias voltages for the PGAs are provided via the microcontroller, or alternatively can be fed by an external lab grade supply to further improve on the (already high) supply noise rejection from the first stage PGA. The proposed hardware is designed to interface with VDI zero bias detectors, high responsivity and low NEP diodes (around 2000 V/W and below 12 pW/√Hz, respectively) operating in monomodal waveguide bands up to 500 GHz. In this contribution we demonstrate the usage of the developed hardware with WR10, WR6.5, WR5 and WR 3 ZBD diodes.@en

In this contribution we present an approach to reduce the error arising from the variations of the lumped load, due to process spread, in probe level calibrations. First, full-wave electromagnetic (EM) simulations are employed to generate the nominal standard responses, then a parametric EM simulation of the load structure is used to generate a parametrized model of the standard. The approach is tested using a Short-Open-Load-Reciprocal calibration algorithm and an impedance standard calibration substrates developed on a 150 mm Quartz wafer (400 pm thick). In this process the high fidelity of the lateral dimension of the fabricated structures, realized using IC Photolithography, allows to confine the variations of the load response to only the thin-film resistor thickness spread. The DC response of the load, measured during the calibration step, is used to identify the specific RF response of the probed load from the parametric model. A complete analysis using full-wave EM simulations accounting for process variation is presented together with a set of experimental data up to 67GHz.@en

In this contribution, we describe the modeling approaches and the characterization procedures used to develop accurate standard models for cryogenic, probe-level, calibrations substrates.The key electrical and mechanical parameters of the impedance terminations and the lines used in commercially available impedance standard substrates are first characterized versus temperature. After, these component are simulated using 2.5D EM solvers including their mechanical variation when exposed to cryogenic temperatures, to extract their nominal response at 7 Kelvin. The quality of the resulting calibrations at cryogenic is evaluated first using independent CPW lines on the calibration substrates and then by measuring the response of a transformer-based resonator realized on a Si-based technology.Ambient temperature models are used as a comparison, to highlight the accuracy improvement that can be achieved employing optimized Cryo-EM based models.

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